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Preliminary
Single-Chip 8-BIT CMOS Microcontroller M37640E8-XXXFP Specification
Ver 1.04
MITSUBISHI SEMICONDUCTOR AMERICA, INC.
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
This publication, or any parts thereof, may not be reproduced in any form without the prior written permission of Mitsubishi Semiconductor America, Inc. (MSAI). The product(s) described in this publication are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use this product for any such unintended or unauthorized application, Buyer shall indemnify and hold MSAI and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that MSAI was negligent regarding the design and manufacture of the part. Information supplied by MSAI is believed to be accurate and reliable. MSAI assumes no responsibility for any errors that may appear in this publication. MSAI reserves the right, without notice, to make changes in device design or specifications. Product is subject to availability. (c)1997 Mitsubishi Semiconductor America, Inc.
Rev. Rev. Rev. Rev. Rev.
1.0 Internal Release 1.01 Design Spec Updates 1.02 Design Spec Updates 1.03 Internal Spec Updates 1.04 Design Spec Updates
April 2, 1997 July 1, 1997 August 28, 1997 Jan. 22, 1998 June 2, 1998
6/2/98
7600 Series M37640E8-XXXFP Specification
Mitsubishi Semiconductor Corporation
2.9.1 USB Function Control Unit (USB FCU).... 2-50 2.9.1.1 Serial Interface Engine ......................... 2-50 2.9.1.2 Generic Function Interface ................... 2-50 2.9.1.3 Serial Engine Interface Unit ................. 2-50 2.9.1.4 Microcontroller Interface Unit.............. 2-50 2.9.1.5 USB Transceiver................................... 2-50 2.9.2 USB Interrupts............................................ 2-51 2.9.2.1 USB Function Interrupt ........................ 2-51 2.9.2.2 USB SOF Interrupt ............................... 2-52 2.9.3 USB Endpoint FIFOs.................................. 2-52 2.9.3.1 IN (Transmit) FIFOs............................. 2-52 2.9.3.2 Out (Receive) FIFOs............................. 2-53 2.9.4 USB Special Function Registers................. 2-54 2.10 Master CPU Bus Interface.............................. 2-65 2.10.1 Data Bus Buffer Status Registers (DBBS0, DBBS1)....................................... 2-68 2.10.2 Input Data Bus Buffer Registers (DBBIN0, DBBIN1)................................... 2-68 2.10.3 Output Data Bus Buffer Registers (DBBOUT0, DBBOUT1)........................... 2-68 2.11 Direct Memory Access Controller.................. 2-69 2.11.1 Operation .................................................. 2-70 2.11.1.1 Source, Destination, and Transfer Count Register Operation ............................................ 2-71 2.11.1.2 DMAC Transfer Request Sources ...... 2-71 2.11.1.3 Transfer Features for USB and MBI .. 2-72 2.11.1.4 DMAC Transfer Mode ....................... 2-74 2.11.1.5 DMAC Transfer Timing ..................... 2-74 2.12 Special Count Source Generator .................... 2-79 2.12.1 SCSG Operation ....................................... 2-79 2.12.2 SCSG Description..................................... 2-80 2.12.2.1 SCSG1 ................................................ 2-80 2.12.2.2 SCSG2 ................................................ 2-80 2.13 Timers............................................................. 2-82 2.13.1 Timer X..................................................... 2-82 2.13.1.1 Read and Write Method...................... 2-82 2.13.1.2 Count Stop Control ............................. 2-83 2.13.1.3 Timer Mode ........................................ 2-83 2.13.1.4 Pulse Output Mode ............................. 2-83 2.13.1.5 Event Counter Mode........................... 2-84 2.13.1.6 Pulse Width Measurement Mode........ 2-84 2.13.2 Timer Y..................................................... 2-84 2.13.2.1 Read and Write Method...................... 2-85 2.13.2.2 Count Stop Control ............................. 2-85 2.13.2.3 Timer Mode ........................................ 2-85 2.13.2.4 Pulse Period Measurement Mode ....... 2-86 2.13.2.5 Event Counter Mode........................... 2-86 2.13.2.6 HL Pulse-width Measurement Mode.. 2-86 2.13.3 Timer 1 ..................................................... 2-87 2.13.3.1 Timer Mode ........................................ 2-87 2.13.3.2 Pulse Output Mode ............................. 2-87 2.13.4 Timer 2 ..................................................... 2-88 2.13.4.1 Timer Mode ........................................ 2-88 2.13.4.2 Pulse Output Mode ............................. 2-88
1 Overview
1.1 MCU Features .................................................... 1-5 1.2 Pin Description and Layout ................................ 1-6
2 Functional Description
2.1 Central Processing Unit...................................... 2-3 2.1.1 Register Structure ......................................... 2-3 2.1.2 Accumulator (A)........................................... 2-3 2.1.3 Index Registers X and Y............................... 2-4 2.1.4 Stack Pointer................................................. 2-4 2.1.5 Program Counter .......................................... 2-4 2.1.6 Processor Status Register ............................. 2-5 2.2 CPU Mode Registers .......................................... 2-7 2.3 Oscillator Circuit ................................................ 2-8 2.3.1 Description ................................................... 2-8 2.3.2 Frequency Synthesizer Circuit ................... 2-11 2.4 Memory Map .................................................... 2-14 2.4.1 Zero page .................................................... 2-15 2.4.2 Special Page................................................ 2-15 2.4.3 Special Function Registers ......................... 2-15 2.5 Processor Modes............................................... 2-17 2.5.1 Single Chip ................................................. 2-17 2.5.2 Memory Expansion .................................... 2-18 2.5.3 Microprocessor ........................................... 2-18 2.5.4 EPROM ...................................................... 2-18 2.5.5 Slow Memory Wait .................................... 2-19 2.5.6 Hold Function ............................................. 2-23 2.5.7 Expanded Data Memory Access ................ 2-23 2.6 Peripheral Interface .......................................... 2-25 2.6.1 Chip Bus Timing ........................................ 2-25 2.6.2 Peripheral Interface and Access Timing..... 2-26 2.7 Input and Output Ports ..................................... 2-28 2.7.1 Ports ............................................................ 2-28 2.7.1.1 I/O Ports................................................ 2-29 2.7.1.2 Power and Ground Pins ........................ 2-40 2.7.1.3 CNVss Pin ............................................. 2-40 2.7.1.4 Xin and Xout Pins ................................. 2-40 2.7.1.5 XCin and XCout Pins ............................ 2-40 2.7.1.6 RESET Pin............................................ 2-40 2.7.1.7 RDY Pin ............................................... 2-41 2.7.1.8 DMAout Pin ......................................... 2-41 2.7.1.9 Fout Pin.................................................. 2-41 2.7.1.10 SYNCout Pin ....................................... 2-41 2.7.1.11 RD and WR Pins................................. 2-41 2.7.1.12 LPF Pin ............................................... 2-41 2.7.1.13 USB D+/D- Pins ................................. 2-41 2.7.1.14 Ext. Cap Pin ........................................ 2-41 2.7.2 Port Control Register .................................. 2-42 2.7.3 Port 2 Pull-up Control Register .................. 2-42 2.8 Interrupt Control Unit....................................... 2-43 2.8.1 Interrupt Control ......................................... 2-43 2.8.2 Interrupt Sequence and Timing .................. 2-47 2.9 Universal Serial Bus ......................................... 2-49
Mitsubishi Semiconductor Corporation
2.13.5 Timer 3 ..................................................... 2-88 2.13.5.1 Timer Mode ........................................ 2-88 2.14 UART ............................................................. 2-90 2.14.1 Baud Rate Selection.................................. 2-91 2.14.2 UART Mode Register............................... 2-93 2.14.3 UART Control Register............................ 2-94 2.14.4 UART Baud Rate Register ....................... 2-94 2.14.5 UART Status Register .............................. 2-94 2.14.6 Transmit/Receive Format ......................... 2-96 2.14.7 Interrupts................................................... 2-98 2.14.8 Clear-to Send (CTSx) and Request-to-Send (RTSx) Signals................ 2-99 2.14.9 UART Address Mode ............................. 2-100 2.15 Serial I/O ...................................................... 2-102 2.15.1 SIO Control Register .............................. 2-102 2.15.2 SIO Operation......................................... 2-102 2.16 Low Power Modes........................................ 2-105 2.16.1 Stop Mode............................................... 2-105 2.16.2 Wait Mode .............................................. 2-106 2.17 Reset ............................................................. 2-107 2.18 Key-On Wake-Up......................................... 2-108
7600 Series M37640E8-XXXFP Specification
3 Electrical Characteristics
3.1 Absolute Maximum Ratings............................... 3-3 3.2 Recommended Operating conditions ................. 3-4 3.3 Electrical Characteristics .................................... 3-6 3.4 Timing Requirements and Switching Characteristics .................................... 3-8
4 Application Notes
4.1 DMAC ................................................................ 4-3 4.1.1 Application ................................................... 4-3 4.2 UART ................................................................. 4-4 4.2.1 Application ................................................... 4-4 4.3 Timer .................................................................. 4-5 4.3.1 Usage ............................................................ 4-5 4.4 Frequency Synthesizer Interface ........................ 4-6 4.5 USB Transceiver ................................................ 4-7 4.6 Ports .................................................................... 4-8 4.7 Programming Notes............................................ 4-9
5 Register List
MITSUBISHI SEMICONDUCTOR AMERICA, INC.
PRELIMINARY
Chapter 1
PRODUCT DESCRIPTION
1 Overview . . . . . . . . . . . . . . . . . . 1-3 1.1 MCU Features . . . . . . . . . . . . 1-5 1.2 Pin Description and Layout . . 1-6
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
1-2
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
1 Overview
The 7600 series, an enhanced family of CMOS 8-bit microcontrollers, offers high-speed operation at low voltage, large internal-memory options, and a wide variety of standard peripherals. The series is code compatible with the M38000, M37200, M37400, and the M37500 series, and provides many performance enhancements to the instruction set. This device is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB) Version 1.0 specification. This device provides data exchange between a USB-equipped host computer and PC peripherals such as telephones, audio systems and digital cameras. See Figure 1-1 for an application system diagram. The USB function control unit can support all four data transfer types listed in the USB specification: Control, Isochronous, Interrupt, and Bulk. Each transfer type is used for controlling a different set of PC peripherals. Isochronous transfers provide guaranteed bus access, a constant data rate, and error tolerance for devices such as computer-telephone integration (CTI) and audio systems. Interrupt transfers are designed to support human input devices (HID) that communicate small amounts of data infrequently. Bulk transfers are necessary for devices such as digital cameras and scanners that communicate large amounts of data to the PC as bus bandwidth becomes free. Finally, control transfers are supported and are useful for bursty, host-initiated type communication where bus management is the primary concern.
4-24 MHz
frequency 48 MHz synthesizer
UART x 2 A0 Bus Interface Control Block S0, S1 Timers
RAM(1K) ROM(32K) 7600 CPU
USB Function Control Unit
DQ(7:0)
Master CPU
RD WR IBF0 OBF0 IBF1 OBF1
Transceiver
D+
SIO DMAC x 2 SCSG
D-
FIFOs (Normal MCU or DMA Transfer) I/O Ports (P0 ~ P8)
Figure 1-1. Application System Diagram
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7600 Series M37640E8-XXXF Preliminary Specification
Table 1-1. Device Feature List Parameter Number of basic instructions Instruction execution time (minimum) Clock frequency (maximum) Clock multiplier option Memory size Input/Output ports ROM RAM 71
Mitsubishi Microcomputers
Function Description 83ns at = 12 MHz (setting to less than 5MHz is NOT recommended) Xin = 48 MHz, XCin = 5 MHz (square wave), = 12 MHz External clock Xin and XCin can be selectively divided and multiplied by X to create system internal clock 32K bytes 1K bytes
P0~P3, P5, P6, I/O 8-bit X 7 (Port 2 has a key-on wake-up feature) P8 P4, P7 I/O 5-bit X 2 FIFO: Endpoint 0: Endpoint 1: Endpoint 2: Endpoint 3: Endpoint 4: IN 16-byte OUT 16-byte IN 512-byteOUT 800-byte IN 32-byte OUT 32-byte IN 16-byte OUT 16-byte IN 16-byte OUT 16-byte
USB Function Control
Master CPU bus interface Special Count Source Generator(SCSG) UART X 2 Serial I/O Timers DMAC Software selectable slew rate control Interrupts Supply voltage External memory expansion External Data Memory Access (EDMA) Device structure Package Operating temperature range
DQ(7:0), R(E), W(R/W), S0, S1, A0, IBF0, OBF0, IBF1, OBF1; total of 17 signals interface with master CPU (Intel 8042-like interface) Baud rate synthesizer 7/8/9-bit character length, with CTS, RTS available 8-bit clock synchronous serial I/O, supports both master and slave modes 8-bit X 3, 16-bit X 2 2 channels, 16 address lines, support single byte or burst transfer modes Ports P0 ~ P8 4 external, 19 internal, 1 software, 1 system interrupts Vcc = 4.15 ~ 5.25V Memory Expansion and Microprocessor mode Allows > 64 Kbyte data access for instruction LDA (indY) and STA (indY) CMOS 80P6N -20 to 85oC
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
1.1
MCU Features
* 7600 8-bit CPU core, CMOS process * Minimum instruction execution time of 83ns (1-cycle instruction @ = 12 MHz) * Efficient software support (C and/or Assembly) * ROM: 32 KB on-chip * RAM: 1 KB on-chip * Built-in Microprocessor or Memory-expansion modes * Three slow memory wait modes: Software Wait, RDY Wait, and Extended RDY Wait * Nine I/O Ports, total 66 programmable I/O pins available * Programmable direction control on every I/O pin * Software selectable slew rate control on every I/O pin * Master CPU Bus Interface: * MCU can be operated in slave mode by control signals from the host CPU * 8 data lines (DQ7-DQ0) and R(E), W(R/W), A0, S0, S1, IBF0, OBF0, IBF1, OBF1 signals available * Master CPU sends and receives data, command, and status by means of DQ7-DQ0 * USB Function Control Unit * USB Transceiver (conforms to USB V1.0 Specification) * DMA * * * * * Controller: Two DMA channels available 16 address lines for 64K byte address space Single byte or burst transfer modes Transfer request by external pins, software triggers or built-in peripherals Maximum 6M byte/sec transfer speed (in burst mode)
* Timers: three 8-bit timers and two 16-bit timers available * Two full duplex UARTs available * One master/slave clock synchronous I/O (SIO), internal or external clock selectable * Built-in Special Count Source Generator (SCSG): can be a clock source for Timer X, UARTs, and SIO * Power-saving wait (IDLE) and stop (powerdown) modes.
MCU Features
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
1.2
Pin Description and Layout
P12/[AB10] P14/[AB12] P13/[AB11] P15/[AB13] P16/[AB14] P17/[AB15] 40 39 38 37 P20/[DB0] P22/[DB2] P24/[DB4] P26/[DB6] P00/[AB0] P02/[AB2] P04/[AB4] P06/[AB6] P21/[DB1] P23/[DB3] P25/[DB5] P27/[DB7] P01/[AB1] P03/[AB3] P05/[AB5] P07/[AB7] P10/[AB8] P11/[AB9]
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P74/OBF1 P73/IBF1/HLDA P72/S1 P71/(HOLD) P70/(SOF) USB D+ USB DExt. Cap Vss Vcc P67/DQ7 P66/DQ6 P65/DQ5 P64/DQ4 P63/DQ3 P62/DQ2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 P61/DQ1 2 P60/DQ0 3 P57/W(R/W) 4 P56/R(E) 5 P55/A0 6 P54/S0 7 P53/IBF0 8 P52/OBF0 9 CNVss 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AVcc Vcc RESET LPF Xin Xout AVss P42/INT1 P51/Tout/XCout P41/INT0 P40/[EDMA] P44/CNTR1 P43/CNTR0 P50/XCin Vss P30/[RDY] P31 P32 P33/[DMAout] P34/[out] P35/[SYNCout] P36/[WR] P37/[RD] P80/UTXD2/SRDY P81/URXD2/SCLK P82/CTS2/SRXD P83/RTS2/STXD P84/UTXD1 P85/URXD1 P86/CTS1 P87/RTS1
M37640E8-XXXFP
[ ]Indicates function in memory expansion and microprocessor modes
36 35 34 33 32 31 30 29 28 27 26 25
Figure 1-2. Pin Layout
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Pin Description and Layout
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Table 1-2. Pin Description
Name
I/O
Description
Pin # 56-41 64-57 40 39 38 37 36 35 34
P00/AB0 CMOS I/O port (address bus). When the MCU is in memory expansion or microprocessor mode, these pins I/O ~ P17/AB15 function as the address bus. P20/DB0 ~ P27/DB7 P30/RDY P31 I/O I/O CMOS I/O port (data bus). When the MCU is in memory expansion or microprocessor mode, these pins function as the data bus. These pins may also be used to implement the Key-on Wake up function. CMOS I/O port (Ready). When the MCU is in memory expansion or microprocessor mode, this pin functions as RDY (hardware wait cycle control).
I/O CMOS I/O port.
CMOS I/O port. When the MCU is in EPROM program mode, the pin is used as VRFY (EPROM memory P32/(VRFY) I/O verify). CMOS I/O port (DMAout). When the MCU is in memory expansion or microprocessor mode, this pin is set to a P33/DMAout I/O "1" during a DMA transfer. When the MCU is in EPROM program mode, the pin is used as PGM (EPROM /PGM memory program). P34/out I/O CMOS I/O port (). When the MCU is in memory expansion or microprocessor mode, this pin becomes out pin. CMOS I/O port (SYNC output). When the MCU is in memory expansion or microprocessor mode, this pin becomes the SYNCout pin.
P35/SYNCout I/O
CMOS I/O port. (WR output). When the MCU is in memory expansion or microprocessor mode, this pin P36/WR/(CE) I/O becomes WR. When the MCU is in EPROM program mode, the pin is used as CE (EPROM memory chip enable). CMOS I/O port. (RD output). When the MCU is in memory expansion or microprocessor mode, this pin P37/RD/(OE) I/O becomes RD. When the MCU is in EPROM program mode, the pin is used as OE (EPROM memory output enable). P40/EDMA P41/INT0 ~ P42/INT1 I/O I/O CMOS I/O port (EDMA: Expanded Data Memory Access). When the MCU is in memory expansion or microprocessor mode, this pin can become the EDMA pin. CMOS I/O port or external interrupt ports INT0 and INT1. These external interrupts can be configured to be active high or low.
33 24 23-22 21
CMOS I/O port or Timer X input pin for pulse width measurement mode and event counter mode or Timer X P43/CNTR0 I/O output pin for pulse output mode. This pin can also be used as an external interrupt when Timer X is not in output mode. The interrupt polarity is selected in the Timer X mode register. CMOS I/O port or Timer Y input pin for pulse period measurement mode, pulse H-L measurement mode and P44/CNTR1 I/O event counter mode or Timer Y output pin for pulse output mode. This pin can also be used as an external interrupt when Timer Y is not in output mode. The interrupt polarity is selected in the Timer Y mode register. P50/XCin P51/Tout/ XCout P52/OBF0 P53/IBF0 P54/S0 P55/A0 P56/R(E) P60/DQ0 ~ P67/DQ7 USB DUSB D+ P70/SOF P71/HOLD P72/S1 I/O CMOS I/O port or XCin. I/O CMOS I/O port or Timer 1/2 pulse output pin (can be configured initially high or initially low), or XCout. I/O CMOS I/O port or OBF0 output to master CPU for data bus buffer 0. I/O CMOS I/O port or IBF0 output to master CPU for data bus buffer 0. I/O CMOS I/O port or S0 input from master CPU for data bus buffer 0. I/O CMOS I/O port or A0 input from master CPU. I/O CMOS I/O port or R(E) input from master CPU.
20 12 11 8 7 6 5 4 3 2-1, 80-75 71 70 69 68 67
P57/W(R/W) I/O CMOS I/O port or W(R/W) input from master CPU. I/O CMOS I/O port or master CPU data bus. I/O USB D- voltage line interface, a series resistor of 33 should be connected to this pin. (see note) I/O USB D+ voltage line interface, a series resistor of 33 should be connected to this pin. (see note) I/O CMOS I/O port or USB start of frame pulse output, an 80 ns pulse outputs on this pin for every USB frame. I/O CMOS I/O port or HOLD pin. I/O CMOS I/O port or S1 input from master CPU for data bus buffer 1.
Pin Description and Layout
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7600 Series M37640E8-XXXF Preliminary Specification
Table 1-2. Pin Description Name P73/IBF1/ HLDA P74/OBF1 I/O Description
Mitsubishi Microcomputers
Pin # 66 65 32 31 30 29 28 27 26 25 17,19 9 16/74, 13/73 10 12 11 14 15 18 72
CMOS I/O port or IBF1 output to master CPU for data bus buffer 1, or HLDA pin. IBF1 and HLDA are I/O mutually exclusive. IBF1 has priority over HLDA. I/O CMOS I/O port or OBF1 output to master CPU for data bus buffer 1.
CMOS I/O port or UART2 pin UTXD2 or SIO pin SRDY. UART2 and SIO are mutually exclusive, UART2 has P80/UTXD2/ I/O priority over SIO. SRDY CMOS I/O port or UART2 pin URXD2 or SIO pin SCLK. UART2 and SIO are mutually exclusive, UART2 P81/URXD2/ I/O SCLK has priority over SIO. P82/CTS2/ SRXD P83/RTS2/ STXD I/O I/O CMOS I/O port or UART2 pin CTS2 or SIO pin SRXD. UART2 and SIO are mutually exclusive, UART2 has priority over SIO. CMOS I/O port or UART2 pin RTS2 or SIO pin STXD. UART2 and SIO are mutually exclusive, UART2 has priority over SIO.
P84/UTXD1 I/O CMOS I/O port or UART1 pin UTXD1. P85/URXD1 I/O CMOS I/O port or UART1 pin URXD1. P86/CTS1 P87/RTS1 AVcc,AVss CNVss Vcc,Vss RESET XCin XCout Xin Xout LPF Ext. Cap I/O CMOS I/O port or UART1 pin CTS1. I/O CMOS I/O port or UART1 pin RTS1. I Power supply inputs for analog circuitry AVcc = 4.15~ 5.25V, AVss = 0V I Controls the processor mode of the chip. Normally connected to Vss or Vcc. When the MCU is in EPROM program mode, this pin supplies the programming voltage to the EPROM.
I Power supply inputs: Vcc = 4.15~ 5.25V, Vss = 0V I To enter the reset state, this pin must be kept L for more that 2s (20 cycles under normal Vcc conditions). If the crystal or ceramic resonator requires more time to stabilize, extend this L level time appropriately.
I An external ceramic or quartz crystal oscillator can be connected between the XCin and XCout pins. If an O external clock source is used, connect the clock source to the XCin pin and leave the XCout pin open. Input and output signals to and from the internal clock generation circuit. Connect a ceramic resonator or quartz I crystal between Xin and Xout pins to set the oscillation frequency. If an external clock is used, connect the clock O source to the Xin pin and leave the Xout pin open. O Loop filter for the frequency synthesizer. An external capacitor (Ext. Cap) pin. When the USB transceiver voltage converter is used, a 2f or larger I capacitor should connect between this pin and Vss to ensure proper operation of the USB line driver. The voltage converter is enabled by setting bit 4 of the USB control register (001316) to a "1".
D+/D- Line driver notes: In order to match the USB cable impedance, a series resistor of 33, 1%, 1/8 W should be connected to each USB line; i.e. on D+ (pin 70) and on D- (pin 71). Also, a coupling capacitor with the recommended value of 33pF should be connected between D+ and D- after the 33 series resistors. If the USB line is improperly terminated or not matched, signal fidelity will suffer, resulting in excessive overshoot or undershoot. This will potentially introduce bit errors. VDD/VSS notes: In order to reduce the effects of the inductance of the traces on the board, decoupling capacitors should be connected between pins 73(VSS) and 74(VDD), 13(VSS) and 16(VDD), and 17(AVDD) and 19(AVSS). Recommended values are a 4.7 F in parallel with a 0.1 F.
Pin 73 (VSS)
C1 C2
Pin 13 (VSS)
C1 C2
Pin 17 (AVSS)
C1 C2
Pin 74 (VDD)
Pin 16 (VDD)
Pin 19 (AVDD)
C1 = 4.7 F C2 = 0.1 F
Figure 1-3. VDD/VSS decoupling capacitor connections
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Pin Description and Layout
MITSUBISHI SEMICONDUCTOR AMERICA, INC.
PRELIMINARY
Chapter 2
Functional Description
2.1 Central Processing Unit . . . . . . 2-3 2.2 CPU Mode Registers . . . . . . . . 2-7 2.3 Oscillator Circuit . . . . . . . . . . . . 2-8 2.4 Memory Map . . . . . . . . . . . . . . 2-14 2.5 Processor Modes . . . . . . . . . . 2-17 2.6 Peripheral Interface . . . . . . . . . 2-25 2.7 Input and Output Ports. . . . . . 2-28 2.8 Interrupt Control Unit . . . . . . . 2-43 2.9 Universal Serial Bus . . . . . . . . 2-49 2.10 Master CPU Bus Interface . . 2-65 2.11 Direct Memory Access Controller . . . . . . . . . . . . . 2-69 2.12 Special Count Source Generator . . . . . . . . . . . . . 2-79 2.13 Timers . . . . . . . . . . . . . . . . . . 2-82 2.14 UART . . . . . . . . . . . . . . . . . . . 2-90 2.15 Serial I/O . . . . . . . . . . . . . . .2-102 2.16 Low Power Modes . . . . . . .2-105 2.17 Reset . . . . . . . . . . . . . . . . . .2-107 2.18 Key-On Wake-Up . . . . . . . .2-108
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2 Functional Description
2.1 Central Processing Unit
The central processing unit (CPU) has six registers: * Accumulator (A) * Index Register X (X) * Index Register Y (Y) * Stack Pointer (S) * Processor Status Register (PS) * Program Counter (PC)
2.1.1
Register Structure
7 7 7 7 15 7
Accumulator Index Register X Index Register Y Stack Pointer
0 0 0 0 0
PCH
7
PCL NVTBD I ZC
0
Program Counter Processor Status Register Carry Flag (bit 0) Zero Flag (bit 1) Interrupt Disable Flag (bit 2) Decimal Mode Flag (bit 3) Break Flag (bit 4) Index X Mode Flag (bit 5) Overflow Flag (bit 6) Negative Flag (bit 7)
Figure 2-1. Register Structure
Five of the CPU registers are 8-bit registers. These are the Accumulator (A), Index register X (X), Index register Y (Y), Stack pointer (S), and the Processor Status register (PS). The Program counter (PC) is a 16-bit register consisting of two 8-bit registers (PCH and PCL) (see Figure 2-1.). After a hardware reset, bit 2 (the I flag) of the PS is set high and the values at the addresses FFFA16 and FFFB16 are stored in the PC, but the values of the other bits of the PS and the other registers are undefined. Initialization of undefined registers may be necessary for some programs.
2.1.2
Accumulator (A)
The accumulator is the main register of the microcomputer. Data operations such as data transfer, input/ output, and so forth, are executed mainly through the accumulator.
Central Processing Unit
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.1.3
Index Registers X and Y
Both index registers X and Y are 8-bit registers. In the absolute addressing modes, the contents of these registers are added to the value of the OPERAND to specify the real address. In the indirect X addressing mode, the value of the OPERAND is added to the contents of register X to specify the zero page basic address. The data at the basic address specifies the real address. In the indirect Y addressing mode, the value of the operand specifies a zero page address. The data at this address is added to the contents of register Y to produce the real address. These addressing modes are useful for referencing subroutine tables and memory tables. When the T flag in the processor status register is set high, the value contained in index register X points to a zero page memory location that replaces the accumulator for most accumulator based instructions.
2.1.4
Stack Pointer
The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Select Bit, bit 2 of the CPU Mode Register A. If the Stack Page Select bit is "0", then the RAM in the zero page (addresses 007016 to 00FF16) is used as the stack area. If the stack page select bit is "1" (the default value), then the RAM in one page (addresses 010016 to 01FF16) is used as the stack area. The base of the stack must be set in software, and stack grows towards lower addresses from that point. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 2-2.
2.1.5
Program Counter
The program counter (PC) is a 16-bit register consisting of two 8-bit sub-registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
2-4
7/9/98
Central Processing Unit
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Main Routine .......
Interrupt Request (Note 1)
.......
M(S) (PCh) (S-1) (PCl) (S-1) (PS) (S-1) Interrupt Routine Contents of Processor Status Register Restored on Stack I Flag set high Jump Vector Fetched
Execute JSR
M(S) (S) Return Address Stored on Stack (Note 2) M(S) (S) Subroutine (PCh) (S-1) (PCl) (S-1)
(S) M(S)
Return Address Stored on Stack (Note 2)
.......
(S) M(S) (S)
Execute RTS (S) (PCl) Return Address Restored (S) (PCh) (PC) (S+1) M(S) (S+1) M(S) (PC+1) (S) (PS) (S) (PCl) (S) (PCh)
Execute RTI (S+1) M(S) (S+1) M(S) Return Address Restored (S+1) M(S) Contents of Processor Status Register Restored
Figure 2-2. Register Push and Pop when Servicing Interrupts and Calling Subroutines
Note 1. The condition to enable an interrupt: Interrupt enable bit is set to a "1" and Interrupt inhibit flag (I flag) is a "0". Note 2. When an interrupt occurs, the address of the next instruction to be executed is stored on the stack. When a subroutine is called, the address of (next instruction -1) to be executed is stored on the stack.
2.1.6
Processor Status Register
The processor status (PS) register is an 8-bit register consisting of flags that indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C), Zero (Z), Overflow (V), or the Negative (N) flags. After reset, the I flag is set to a "1", but all other flags are undefined. Because the T and D flags directly affect arithmetic operations, they should be initialized in the beginning of a program. Carry Flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It is also affected by shift and rotate instructions. The C flag can be set directly by the set carry (SEC) instruction and cleared by the clear carry (CLC) instruction.
Central Processing Unit
7/9/98
2-5
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Zero Flag (Z) The Z flag is set if the result of an arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". Interrupt Disable Flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction and any non-maskable interrupts, if available. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to a "1" to prevent other interrupts from interfering until the current interrupt service routine is completed. The I flag can be set by the set interrupt disable (SEI) instruction and cleared by the clear interrupt disable (CLI) instruction. Decimal Mode Flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. The D flag can be set by the set decimal mode (SED) instruction and cleared by the clear decimal mode (CLD) instruction. Break Flag (B) The B flag is used to indicate whether the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is nominally "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to a "1". The saved processor status is the only place where the break flag is ever set. Index X Mode Flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, and the results are stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory and memory, as well as between I/O and I/O. The result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. The T flag can be set by the set T flag (SET) instruction and cleared by the clear T flag (CLT) instruction. Because the T flag directly affects calculations, it should be initialized after a reset. Overflow Flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds the range from +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. The V flag can be cleared by the CLV instruction, but there is no set instruction. In decimal mode, the V flag is invalid. Negative Flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative, that is (bit 7 is "1"). When the BIT instruction is executed, bit 7 of the memory location operated by the BIT instruction is stored in the negative flag. There are no instructions for directly setting or clearing the N flag.
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Central Processing Unit
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.2
CPU Mode Registers
Address
000016 000116
Description
CPU mode register A CPU mode register B
Acronym and Value at Reset CPMA=0C CPMB=83
This device has two CPU mode registers: CPU Mode Register A (CPMA) and CPU Mode Register B (CPMB) that control the processor mode, clock, slow memory wait and other CPU functions. The bit representation of each register is described in Figure 2-3 and Figure 2-4:
MSB 7 CPMA7 CPMA6 CPMA0,1 CPMA5 CPMA4 CPMA3 CPMA2 CPMA1 CPMA0 LSB 0 Address: 000016 Access: R/W Reset: 0C16
CPMA2
CPMA3
CPMA4
CPMA5
CPMA6
CPMA7
Processor Mode Bits (bits 1,0) Bit 1 Bit 0 0 0: Single-Chip Mode 0 1: Memory Expansion Mode 1 0: Microprocessor Mode 1 1: Not used Stack Page Selection Bit (bit 2) 0: In page 0 area 1: In page 1 area Xcout Drive Capacity Selection Bit (bit 3) 0: Low 1: High Clock XCin-XCout Stop Bit (bit 4) 0: Stop 1: Oscillator Clock Xin-Xout Stop Bit (bit 5) 0: Oscillator 1: Stop Internal Clock Selection Bit (bit 6) 0: External Clock 1: fsyn External Clock Selection Bit (bit 7) 0: Xin-Xout 1: XCin-XCout
Figure 2-3. CPU Mode Register A
Address: 000116 Access: R/W Reset: 8316
MSB 7
CPMB7
Reserved
CPMB5
CPMB4
CPMB3
CPMB2
CPMB1
CPMB0
LSB 0
CPMB0,1
CPMB2,3
CPMB4
CPMB5
CPMB6 CPMB7
Slow Memory Wait Bits (bits 1,0) Bit 1 Bit 0 0 0: No wait 0 1: One time wait 1 0: Two time wait 1 1: Three time wait Slow Memory Mode Bit (bits 3,2) Bit 3 Bit 2 0 0: Software wait 0 1: Not used 1 0: Fixed wait by RDY pin L 1 1: Extended RDY wait Expanded Data Memory Access Bit (bit 4) 0: EDMA output disabled (64 Kbyte data access area) 1: EDMA output enabled (greater than 64 Kbytes data access area) HOLD Function Enable Bit (bit 5) 0: HOLD Function Disabled 1: HOLD Function Enabled Reserved (Read/Write "0") Xout Drive Capacity Selection Bit (bit 7) 0: Low 1: High (default state after reset and after STOP mode)
Figure 2-4. CPU Mode Register B
CPU Mode Registers
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.3
2.3.1
Oscillator Circuit
Description
An on-chip oscillator provides the system and peripheral clocks as well as the USB clock necessary for operation. This oscillator circuit is comprised of amplifiers that provide the gain necessary for oscillation, oscillation control logic, a frequency synthesizer, and buffering of the clock signals. A flow diagram for the oscillator circuit is shown in Figure 2-6 and a block diagram of the oscillator circuit is shown in Figure 2-7. The following external clock inputs are supported: * A quartz crystal oscillator of up to 24 MHz, connected to the Xin and Xout pins. * An external clock signal of up to 48 MHz, connected to the Xin pin. * A ceramic resonator or quartz crystal oscillator of 32.768 kHz, connected to the XCin and XCout pins. * An external clock signal of up to 5.12 MHz, connected to the XCin pin. The frequency synthesizer can be used to generate a 48MHz clock signal (fUSB) needed by the USB block and clock fSYN, which can be chosen as the source for the system and peripheral clocks. Both fUSB and fSYN are phase-locked frequency multiples of the frequency synthesizer input. The inputs to the frequency synthesizer can be either Xin or XCin. The two-phase non-overlapping system clock (CPU and peripherals) is derived from the source to the clock circuit and is 1/2 the frequency of the source. (i.e. Source = 24 MHz, system clock = 12 MHz) Any one of four clock signals can be chosen as the source for the system and peripheral clocks; fXin/ 2, fXin, fXCin, or fSYN. The selection is based on the values of bits CPMA6, CPMA7 and CCR7. The default source after reset is fXin/2. The default source for the system and peripheral clocks is fXin/2. If fXin = 24MHz, then the CPU will be running at = 6MHz (low frequency mode. For the CPU to run in high frequency mode, i.e., source of clock = fXin, write a "1" to bit 7 of the clock control register.
MSB 7 CCR7 CCR6 Bits 0-3 CCR4: CCR5 CCR4 Reserved Reserved Reserved Reserved LSB 0 Address: 001F16 Access: R/W Reset: 0016
CCR5:
CCR6:
CCR7:
Reserved (Read/Write "0") PLL Bypass Bit (bit 4) 0: fUSB = fVCO (Frequency synthesizer output) 1: fUSB = fXin XCout Oscillation Drive Disable Bit (bit 5) 0: XCout oscillation drive is enabled (when XCin oscillation is enabled). 1: XCout oscillation drive is disabled. Xout Oscillation Drive Disable Bit (bit 6) 0: Xout oscillation drive is enabled (when Xin oscillation is enabled). 1: Xout oscillation drive is disabled. Xin Divider Select Bit (bit 7) 0: fXin/2 is used for the system clock source when CMPA7:6=00 1: fXin is used for the system clock source when CMPA7:6=00
Figure 2-5. Clock Control Register
The drive strength of the Xout and XCout inverting amplifier can be controlled by bits CPMB7 and CPMA3, respectively. High drive is the default at reset or after executing a STP instruction and must be chosen whenever restarting Xin or XCin oscillation if a ceramic or crystal oscillator is used. When oscillation has been established, low drive can be selected to reduce power consumption. If an external clock signal is input to Xin or XCin, the inverting amplifiers can be disabled by means of the CCR6 and CCR7 bits, respectively, in order to reduce power consumption.
2-8
7/9/98
Oscillator Circuit
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Reset
Stop
Note 1
Xin clock on XCin clock stopped PLL clock stopped
FSC0 1 0
Wait
=f(Xin)/4 Note 2
1 0
Xin clock on XCin clock stopped PLL clock on Note 3
CPMA6 1 0
=f(Xin)/4 Note 2
Xin clock on XCin clock stopped PLL clock on
CPMA=0C, FSC=60
CPMA=0C, FSC=41
=f(PLL)/2
Wait
CPMA=4C, FSC=41
CPMA4 FSC0 1 0 Xin clock on XCin clock on PLL clock on Note CPMA6 1
3
Stop Note 1 Wait
Xin clock on XCin clock on PLL clock stopped
=f(Xin)/4 Note 2
1 0
=f(Xin)/4 Note 2
0
Xin clock on XCin clock on PLL clock on
=f(PLL)/2
Wait
CPMA=1C, FSC=60
CPMA=1C, FSC=41
CPMA=5C, FSC=41
CPMA7 FSC0 1 0 Xin clock on XCin clock on PLL clock on Note CPMA6 1
3
Stop Note 1 Wait
Xin clock on XCin clock on PLL clock stopped
=f(XCin)/2
1
=f(XCin)/2
0
Xin clock on XCin clock on PLL clock on
=f(PLL)/2
Wait
CPMA=9C, FSC=60 0
CPMA=9C, FSC=41
CPMA=DC, FSC=41
CPMA5 Note 4 FSC0 1 0 Xin clock stopped XCin clock on PLL clock on Note CPMA6 1
3
Stop Note 1 Wait
Xin clock stopped XCin clock on PLL clock stopped
=f(XCin)/2
=f(XCin)/2
0
Xin clock stopped XCin clock on PLL clock on
=f(PLL)/2
Wait
CPMA=BC, FSC=68
CPMA7=BC, FSC=49
CPMA7=FC, FSC=49
Note 1: Stop mode stops the oscillators which are also the inputs to the frequency synthesizer. However, the frequency synthesizer is not disabled and so its output is unstable. So, always set the system clock to an external oscillator and disable the frequency synthesizer before entering stop mode. Note 2: =f(Xin)/4 can be inter-changed with =f(Xin)/2 by setting CCR7 to "1". The same flow-chart applies for both cases. Note 3: The input to the frequency synthesizer is independent of the system clock. It can be either Xin or XCin depending on bit 3 of FSC. In the above flow, the input has been chosen to be the same as the system clock only for simplicity. The oscillator selected to be the input to the frequency synthesizer must be enabled before the frequency synthesizer is enabled. Note 4: The input clock for the frequency synthesizer must be set to XCin by setting FIN (bit 3 of FSC) to a "1" before Xin oscillation can be disabled. Note: CPMA values shown assume single-chip mode with stack in one page.
Figure 2-6. Clock Flow Diagram
Oscillator Circuit
7/9/98
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7600 Series M37640E8-XXXF Preliminary Specification
P1HATRSTB P2LATRSTB DQ PIN1 T R DQ PIN2 T R DQ PIN1 T R DQ P2+ T R RQ S DQ PIN1 T
Mitsubishi Microcomputers
RESETB
PadResetB
DQ P2+ T STP P2LATRSTB
P2 Peripheral P1 Peripheral
Oscillator Countdown Timer 1->2 STP
RQ RQ S RQ STP S
DQ T P1HATRSTB DQ
P2 Peripheral
P1 Peripheral P2 Out P1 Out R P2LATRSTB out
S
Q
Interrupt Request I Flag PadResetB STP XOSCSTP Delay
S R QB
WIT S
PIN2
T
DQ OSCSTP CPMA5 XOD XDOSCSTP XCOD XCDOSCSTP CCR7 fXin XCOSCSTP CPMA4 PIN1,PIN2 CPMB0 CPMB1 CPMB2 CPMB3 Slow Memory Wait P1+,P2+ P1HATRSTB P2+ T
P2
P1
RDY
LPF
XOSCSTP CPMB7
1/2
CPMA7
LPF
XCOSCSTP
fXCin FIN(FSC3) fIN Frequency Synthesizer
enable
CPMA5
CPMA3 CPMA4
fEXT CPMA6 fSYN 1/2
Xin
Xout
XCin
XCout
FSC0
LPF CCR4
USB 48MHz clock
Figure 2-7. Clock Block Diagram
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7/9/98
Oscillator Circuit
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.3.2
Frequency Synthesizer Circuit
The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock fSYN that are both a multiple of the external input reference clock fIN. A block diagram of the circuit is shown in Figure 2-8.
fIN
Prescaler
fPIN
Frequency Multiplier
fVCO
Frequency Divider
fSYN fUSB
8 Bit
8 Bit
LS 8 Bit
FSM2
006E
FSM1
006D
FSC
006C
FSD
006F
Data Bus Figure 2-8. Frequency Synthesizer Circuit
The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider macro, and four registers, namely FSM1, FSM2, FSC and FSD. Two multiply registers (FSM1, FSM2) control the frequency multiply amount. Clock fIN is prescaled using FSM2 to generate fPIN. fPIN is multiplied using FSM1 to generate an fVCO clock which is then divided using FSD to produce the clock fSYN. The fVCO clock is optimized for 48 MHz operation and is buffered and sent out of the frequency synthesizer block as signal fUSB. This signal is used by the USB block. Clock fPIN is a divided down version of clock fIN, which can be either fXin or fXCin. The default clock after reset is fXin. The relationship between fPIN and the clock input to the prescaler (fIN) is as follows: * fPIN = fIN / 2(n+1) where n is a decimal number between 0 and 254. Setting FSM2 to 255 disables the prescaler and fPIN = fIN.
MSB 7 Bit 7 Bit 6 Bit 5 Bit 4 FSM2 Dec(n) 255 11 5 3 1 Hex(n) FF 0C 05 03 01 Bit 3 Bit 2 Bit 1 Bit 0 LSB 0 Address: 006E16 Access: R/W Reset: fIN 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz FF16
fPIN 24 MHz 1 MHz 2 MHz 3 MHz 6 MHz 12 MHz
0 00 fIN/2(n+1) = fPIN
Figure 2-9. Frequency Synthesizer Multiply Control Register FSM2
Oscillator Circuit
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB 7
Bit 7
Bit 6 fPIN
Bit 5
Bit 4 FSM1 Dec(n) 74 11 5 3 1
Bit 3
Bit 2
Bit 1 fVCO
Bit 0
Address: 006D16 LSB Access: R/W 0 Reset: FF16
Hex(n) 4A 0B 05 03 01
320 kHz 2 MHz 4 MHz 6 MHz 12 MHz 24 MHz
48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz
0 00 fVCO/2(n+1) = fPIN
Figure 2-10. Frequency Synthesizer Multiply Control register FSM1
MSB 7
Bit 7
Bit 6 fVCO
Bit 5
Bit 4 FSD Dec(m) 00
Bit 3
Bit 2
Bit 1 fSYN
Bit 0
LSB Address: 006F16 0 Access: R/W Reset: FF16
Hex(m) 00
48.00 MHz 48.00 MHz
24.00 MHz 187.50 KHz
127 7F fVCO/2(m+1) = fSYN
Figure 2-11. Frequency Synthesizer Divide Register
The relationship between fPIN, fVCO, and fSYN is as follows: * fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM2, FSM1. Note: n must be chosen such that fVCO equals 48 MHz.
* fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD Note: Setting m = 255 disables the divider and disables fSYN.
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled (FSC0 = "0"), fVCO is held at either a high or low state. When the frequency synthesizer control bit is active (FSC0 = "1"), a lock status (LS = "1") indicates that fSYN and fVCO are the correct frequency. The LS and FSCO control bits in the FSC Control register are shown in Figure 2-12. When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin. Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that none of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable.
2-12
7/9/98
Oscillator Circuit
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
LS
CHG1 FSE
CHG0
Reserved
FIN
VCO1
VCO0
FSE
LSB 0
VCO1,0
FIN
Bit 4 CHG1,0
LS
Frequency Synthesizer Enable Bit (bit 0) 0: Disabled 1: Enabled VCO Gain Control (bits 2,1) Bit 2 Bit 1 0 0: Lowest Gain (recommended) 0 1: Low Gain 1 0: High Gain 1 1: Highest Gain Frequency Synthesizer input selector Bit (bit 3) 0: Xin 1: XCin Reserved (Read/Write "0") LPF Current Control (bits 6,5) Bit 6 Bit 5 0 0: Disabled 0 1: Low Current 1 0: Intermediate Current (recommended) 1 1: High Current Frequency Synthesizer Lock Status Bit (bit 7) (Read Only; Write "0") 0: Unlocked 1: Locked
Address: 006C16 Access: R/W Reset: 6016
Figure 2-12. Frequency Synthesizer Control Register
Oscillator Circuit
7/9/98
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.4
Memory Map
000016 SFR Area Zero Page RAM 00FF16 010016 1K bytes 046F16 047016 006F16 007016
Not Used
7FFF16 800016 Reserved Area 807F16 808016 ROM 32K bytes FEFF16 FF0016 FFC916 FFCA16 Special page for subroutine calls Reserved Area FFFF16 FFFB16 FFFC16
Figure 2-13. Memory Map
The first 112 bytes of memory from 000016 to 006F16 is the special function register (SFR) area and contains the CPU mode registers, interrupt registers, and other registers to control peripheral functions (see Figure 2-13.). The general purpose RAM resides from 007016 to 046F16. When the MCU is in memory expansion or microprocessor mode and external memory is overlaid on the internal RAM, the CPU reads data from the internal RAM. However, the CPU writes data in both the internal and external memory. The area from 047016 to 7FFF16 is not used in single-chip mode, but can be mapped for an external memory device when the MCU is in memory expansion or microprocessor mode. The area from 800016 to 807F16 and from FFFC16 to FFFF16 are factory reserved areas. Mitsubishi uses it for test and evaluation purposes. The user can not use this area in single-chip or memory expansion modes. The user 32K byte ROM resides from 808016 to FFFB16. When the MCU is in microprocessor mode, the CPU accesses an external area rather than accessing the internal ROM. Zero page and special page area can be accessed by 2-byte commands by using special addressing modes. 2-14 7/9/98 Memory Map
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.4.1
Zero page
The 256 bytes zero page area is where the SFR and part of the internal RAM are allocated. The zero page addressing modes can be used to specify memory and register addresses in this area (see Figure 2-14.). These dedicated addressing modes enable access to this area with fewer instruction cycles.
Zero Zero Zero Zero Zero Zero Page Page Page Page Page Page (2 byte instruction) Indirect (2 byte instruction) X (2 byte instruction) Y (2 byte instruction) Bit (2 byte instruction) Bit Relative (3 byte instruction)
Addressing Modes for zero page only
Addressing modes in which zero page access is possible
Absolute (3 byte instruction) Absolute X (3 byte instruction) Absolute Y (3 byte instruction) Relative (2 byte instruction) Indirect (3 byte instruction) Indirect X (2 byte instruction) Indirect Y (2 byte instruction)
Addressing modes in which special page access is possible
Special Page (2 byte instruction)
Addressing mode for special page only
Figure 2-14. Zero Page and Special Page Addressing Modes
2.4.2
Special Page
The 256 bytes from address FF0016 to FFFF16 are called the special page area. In this area special page addressing can be used to specify memory addresses (see Figure 2-14.). This dedicated special page addressing mode enables access to this area with fewer instruction cycles. Frequently used subroutines are normally stored in this area.
2.4.3
Special Function Registers
The special function registers (SFR) are used for controlling the functional blocks, such as I/O ports, Timers, UART, and so forth (see Table 2-1.). The reserved addresses should not be read or written to.
Memory Map
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7600 Series M37640E8-XXXF Preliminary Specification
Table 2-1. SFR Addresses
Addr
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716
Mitsubishi Microcomputers
Description
CPU Mode Register A CPU Mode Register B Interrupt Request Register A Interrupt Request Register B Interrupt Request Register C Interrupt Control Register A Interrupt Control Register B Interrupt Control Register C Port P0 Port P0 Direction Register Port P1 Port P1 Direction Register Port P2 Port P2 Direction Register Port P3 Port P3 Direction Register Port Control Register Interrupt Polarity Selection Register Port P2 pull-up Control Register USB Control Register Port P6 Port P6 Direction Register Port P5 Port P5 Direction Register Port P4 Port P4 Direction Register Port P7 Port P7 Direction Register Port P8 Port P8 Direction Register Reserved Clock Control Register Timer XL Timer XH Timer YL Timer YH Timer 1 Timer 2 Timer 3 Timer X Mode Register Timer Y Mode Register Timer 123 Mode Register SIO Shift Register SIO Control Register 1 SIO Control Register 2 Special Count Source Generator1 Special Count Source Generator2 Special Count Source Mode Register UART1 Mode Register UART1 Baud Rate Generator UART1 Status Register UART1 Control Register UART1 Transmit/Receiver Buffer 1 UART1 Transmit/Receiver Buffer 2 UART1 RTS Control Register Reserved
Acronym and Value at Reset
CPMA=0C CPMB=03 IREQA=00 IREQB=00 IREQC=00 ICONA=00 ICONB=00 ICONC=00 P0=00 P0D=00 P1=00 P1D=00 P2=00 P2D=00 P3=00 P3D=00 PTC=00 IPOL=00 PUP2=00 USBC=00 P6=00 P6D=00 P5=00 P5D=00 P4=00 P4D=00 P7=00 P7D=00 P8=00 P8D=00
Addr
003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616
Description
UART2 Mode Register UART2 Baud Rate Generator UART2 Status Register UART2 Control Register UART2 Transmit/Receiver Buffer 1 UART2 Transmit/Receiver Buffer 2 UART2 RTS Control Register DMAC Index and Status Register DMAC Channel x Mode Register 1 DMAC Channel x Mode Register 2 DMAC Channel x Source Register Low DMAC Channel x Source Register High DMAC Channel x Destination Register Low DMAC Channel x Destination Register High DMAC Channel x Count Register Low DMAC Channel x Count Register High Data Bus Buffer register 0 Data Bus Buffer status register 0 Data Bus Buffer Control Register 0 Reserved Data Bus Buffer register 1 Data Bus Buffer Status Register 1 Data Bus Buffer Control Register 1 Reserved USB Address Register USB Power Management Register USB Interrupt Status Register 1 USB Interrupt Status Register 2 USB Interrupt Enable Register 1 USB Interrupt Enable Register 2 USB Frame Number Register Low USB Frame Number Register High USB Endpoint Index USB Endpoint x IN CSR USB Endpoint x OUT CSR USB Endpoint x IN MAXP USB Endpoint x OUT MAXP USB Endpoint x OUT WRT_CNT Low USB Endpoint x OUT WRT_CNT High Reserved USB Endpoint 0 FIFO USB Endpoint 1 FIFO USB Endpoint 2 FIFO USB Endpoint 3 FIFO USB Endpoint 4 FIFO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Freq Synthesizer Control Freq Synthesizer Multiply Register 1 Freq Synthesizer Multiply Register 2 Freq Synthesizer Divide Register
Acronym and Value at Reset
U2MOD=00 U2BRG=XX U2STS=03 U2CON=00 U2TRB1=XX U2TRB2=XX U2RTSC=80 DMAIS=00 DMAxM1=00 DMAxM2=00 DMAxSL=00 DMAxSH=00 DMAxDL=00 DMAxDH=00 DMAxCL=00 DMAxCH=00 DBB0=00 DBBS0=00 DBBC0=00
DBB1=00 DBBS1=00 DBBC1=00
USBA=00 USBPM=00 USBIS1=00 USBIS2=00 USBIE1=00 USBIE2=00 USBSOFL=00 USBSOFH=00 USBINDEX=00 IN_CSR=00 OUT_CSR=00 IN_MAXP=00 OUT_MAXP=00 WRT_CNTL=00 WRT_CNTH=00
CCR=00 TXL=FF TXH=FF TYL=FF TYH=FF T1=FF T2=01 T3=FF TXM=00 TYM=00 T123M=00 SIOSHT=XX SIOCON1=00 SIOCON2=18 SCSG1=FF SCSG2=FF SCSM=00 U1MOD=00 U1BRG=XX U1STS=03 U1CON=00 U1TRB1=XX U1TRB2=XX U1RTSC=80
005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16
USBFIFO0=N/A USBFIFO1=N/A USBFIFO2=N/A USBFIFO3=N/A USBFIFO4=N/A
FSC=60 FSM1=FF FSM2=FF FSD=FF
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Memory Map
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.5
Processor Modes
The operation modes are described below. The memory maps for the first three modes are shown in Figure 2-15. Single chip mode is normally entered after reset. However, if the MCU has a CNVss pin, holding this pin high will cause microprocessor mode to be entered after reset. After the reset sequence has completed, the mode can be changed with software by modifying the value of bits 0 and 1 of CPMA. However, while CNVss is high, bit 1 of CPMA is "1" and cannot be changed.
Single Chip Mode
0000 0007 0008 000F 0010 006F 0070 Internal RAM (Zero Page) 00FF 0100 Internal RAM 046F 0470 046F 0470 CPMA, CPMB,& Int Registers P0-P3 SFR 000F 0010 006F 0070 00FF 0100 Internal RAM 046F 0470
Memory Expansion Mode
0000 0007 0008 CPMA, CPMB,& Int Registers External Memory SFR 000F 0010 006F 0070 0000 0007 0008
Microprocessor Mode
CPMA, CPMB,& Int Registers External Memory SFR
Internal RAM (Zero Page)
Internal RAM (Zero Page)
00FF 0100 Internal RAM
Inaccessible Area
External Memory
7FFF 8000 807F 8080 Reserved Area
7FFF 8000 807F 8080
Reserved Area
External Memory
ROM FFC9 FFCA Interrupt Vectors FFFB FFFC FFFF Reserved Area FFFF FFFB FFFC FFC9 FFCA
ROM
Interrupt Vectors
Reserved Area FFFF
Figure 2-15. Operation Modes Memory Maps
2.5.1
Single Chip
In this mode, all ports take on their primary function and all internal memory is accessible. Those areas that are not in internal memory are not accessible. Also, slow memory wait and EDMA are disabled in this mode.
Processor Modes
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Mitsubishi Microcomputers
2.5.2
Memory Expansion
In this mode, Ports 0 and 1 output the address bus (AB0-AB15), port 2 acts as the data bus input and output, and port 3 bits 7 to 3 output RD, WR, SYNCout, out, and DMAout, respectively. All memory areas that are not internal memory or SFR area are accessed externally. Because ports 0 to 3 lose their normal function in this mode, the address area for the ports and their direction registers are treated as external memory (see Figure 2-15.) In this mode, slow memory wait and EDMA can be enabled.
2.5.3
Microprocessor
This mode is primarily the same as memory expansion mode. The difference is that the internal ROM / EPROM area can not be accessed and is instead treated as external memory. Slow memory wait and EDMA can be enabled in this mode.
2.5.4
EPROM
This mode is used for programming and testing the internal EPROM. In this mode, ports 0 and 1 input the address, port 2 acts as the data bus input and output, and port 3 bits 7, 6, 3 and 2 input OEB, CEB, PGMB, and VRFY, respectively.
CPMA1 CPMA0
Port Mode
0 0
1 0
0 1
Single Chip Mode
Internal Port P07 - P00
I/O Port
Microprocessor Mode
Internal Port P07 - P00
Address Output
Memory Expansion Mode
Port P0
Same as Microprocessor Mode
AB7 - AB0 Internal Internal Port P17 - P10
I/O Port
Port P1
Port P17 - P10
Address Output
Same as Microprocessor Mode
AB15 - AB8 Internal Internal Port P27 - P10
I/O Port
Port P2
Port P27 - P20
Data I/O
Same as Microprocessor Mode
DB7 - DB0 Internal Port P37 - P30 Internal
I/O Port
Port 34
Port 37
RD Output
Port P3
Port 36
WR Output
Same as Microprocessor Mode
Port 35
SYNCout DMAout Output
Port 33
Figure 2-16. Function of Ports P0-P3 in each Processor Mode
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.5.5
Slow Memory Wait
The wait function is used when interfacing with external memories that are too slow to operate at the normal read/write speed of the MCU. When this is the case, a wait can be used to extend the read/ write cycle. Three different wait modes are supported; software wait, RDY wait, and extended RDY wait. The appropriate mode is chosen by the setting of bits 0 to 3 of CPMB. The wait function is disabled for internal memory and is valid only for memory expansion and microprocessor modes. Software wait is used to extend the read/write cycle by one, two, or three cycles. The cycle number is determined by the value of bits 0 and 1 of the CPMB. When software wait is selected, the value on the RDY pin is ignored. The timing for software wait is shown in Figure 2-17. RDY wait is also used to extend the read/write cycle by one, two, or three cycles. In this case, the read/write cycle is extended if the RDY pin is low a specific amount of time prior to out going low at the beginning of the read/write cycle. The extension time is fixed by the value of bits 0 and 1 of CPMB and does not depend on the state of the RDY pin when the read/write cycle has begun. If the RDY pin is high at the specified time prior to out going low at the beginning of the read/write cycle, the cycle is not extended. The timing for RDY wait is shown in Figure 2-18.. The extended RDY wait mode is used to extend the read/write cycle by one, two, or three cycles, and then by an additional amount, dependent on the state of the RDY pin. In this mode, initial extension is identical to that of the RDY wait. The state of the RDY pin is checked a specific amount of time prior to the completion of the first cycle of the read/write extension. If the RDY pin is low, the extension is re-initiated from the time that out goes low at the end of the first cycle of the read/ write extension. The RDY pin continues to be checked until it is brought high. When the RDY pin is brought high, the wait is no longer re-initiated when out goes low, and the read/write cycle completes in one, two, or three cycles, dependent on the value in bits 0 and 1 of CPMB. The timing for this mode is shown in Figure 2-19. The wait function can only be enabled for external memory access in microprocessor or memory expansion modes. However, the wait function can not be enabled for accesses to addresses 000816 to 000F16 (port 0 through port 3 direction registers) in these modes, even though the locations are mapped as external memory.
Processor Modes
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2-20
In Out In Out In Out
Xin
P1
P2
out
ADout
7600 Series M37640E8-XXXF Preliminary Specification
DBin/out
RD
WR
No Wait One Time S/W Wait CPMB = 0116 CPMB = 0016 Two Time S/W Wait CPMB = 0216
RDY
Figure 2-17. Software Wait Timing Diagram
7/9/98
In Out
Xin
P1
P2
out
ADout
DBin/out
RD
WR
Three Time S/W Wait CPMB = 0316
Mitsubishi Microcomputers
RDY
Internal
Signals
Processor Modes
Xin
Processor Modes
Out Out In Out In
P1
P2
out
ADout
Mitsubishi Microcomputer
DBin/out
In
RD
tsu tsu tsu tsu
WR
RDY
No Wait CPMB = 0916 CPMB = 0A16 One Time Fixed Wait Two Time Fixed Wait
Figure 2-18. RDY Wait Timing Diagram
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In Out
Xin
CPMB = 0816
P1
P2
out
ADout
DBin/out
RD
tsu
tsu
WR
Three Time Fixed Wait CPMB = 0B16
RDY Internal Signals
7600 Series M37640E8-XXXF Preliminary Specification
2-21
2-22
In Out In In Out
Xin
P1
P2
out
ADout
DBin/out
RD
tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu tsu
7600 Series M37640E8-XXXF Preliminary Specification
WR
RDY
No Wait CPMB = 0C16 CPMB = 0D16 One Time Extended RDY Wait Two Time Extended RDY Wait CPMB = 0E16
Figure 2-19. Extended RDY Wait Timing Diagram
7/9/98
Out In
Xin
P1
P2
out
ADout
Out
DBin/out
tsu tsu tsu tsu
RD
tsu
tsu
tsu tsu tsu tsu tsu
tsu
tsu tsu
WR
tsu tsu tsu
Mitsubishi Microcomputers
RDY
Three Time Extended RDY Wait CPMB = 0F16 CPMB = OE16
Processor Modes
Two Time Extended RDY Wait
Internal Signals
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.5.6
Hold Function
The hold function is used when the MCU is put in a system where more than one device will need control of the external address and data buses. Two signals are used to implement this function, HOLD (P71) and HLDA (P73). HOLD is an input to the MCU and is brought low when an external device wants the MCU to relinquish the address and data buses. HLDA is an output from the MCU that signals when the MCU has relinquished the buses. When this is the case, the MCU tri-state ports 0 and 1 (address bus) and port 2 (data bus), and holds port P37 (RD) and port P36 (WR) high. Ports P37 and P36 are held high to prevent any external device that is enabled by RD or WR from being falsely activated. The clocks to the CPU are stopped, but the peripheral clocks and port P34 (out) continue to oscillate. HOLD is brought high to allow the MCU to regain the address and data buses. When this occurs, HLDA will go high and ports P1, P2, P37 and P36 will begin to drive the external buses again. The timing for the hold function is shown in Figure 2-20. The hold function is only valid for memory expansion and microprocessor modes. Bit 5 of CPMB is used to enable the hold function. HLDA will loose its function when the IBF1 pin functionality is used.
XIN P1 P2 P1PER P2PER out RD, WR ADDRout DATAin/out
tsu(HOLD-out) th(out-HOLD) td(out-HLDA)
HOLD
td(out-HLDA)
HLDA Figure 2-20. Hold Mode Timing Diagram
2.5.7
Expanded Data Memory Access
The Expanded Data Memory Access (EDMA) mode feature allows the user to access a greater than 64 Kbyte data area for instructions LDA (IndY) with T = "0" and T = "1", and STA (IndY). Bit 4 of CPMB is used to enable/disable the EDMA function. If bit 4 of CPMB equals "1", then during the data read/write cycle of instructions LDA (IndY) and STA (IndY) Port 40 (EDMA) is driven low. The EDMA signal output can be used by an external decoder to indicate when the read/write is to a different 64 Kbyte bank. The actual determination of which bank to access can be done by using a few bits of a port to represent the extended addresses above AB15. For example, if four banks are accessed, then two bits are needed to uniquely identify each bank. Two port bits can be used for this, one representing AB16 and the other AB17. The instruction sequences for STA (IndY) and LDA (IndY) are shown in Figure 2-21. and Figure 2-22.
Processor Modes
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SYNCout RD WR Address Data EDMA
PC 91 PC +1 BAL, 00 BAL
BAL+1, 00 ADL+Y,ADH ADL+Y, ADH+C
Mitsubishi Microcomputers
PC + 2 Data Next OpCode
ADL
ADH
Invalid
Figure 2-21. STA ($zz),Y Instruction Sequence with EDMA Enabled
[LDA ($zz),Y (T = "0")] Instruction Sequence (EDMA) SYNCout RD WR Address Data EDMA [LDA ($zz),Y (T = "1")] Instruction Sequence (EDMA) SYNCout RD WR Address Data EDMA Figure 2-22. LDA ($zz),Y Instruction Sequences with EDMA Enabled
PC B1 PC +1 BAL, 00 BAL BAL+1, 00
ADL+Y,ADH ADL+Y, ADH+C ADL+Y, ADH+C
PC B1
PC +1
BAL, 00 BAL
BAL+1, 00
ADL+Y,ADH
PC + 2 Data Next OpCode
ADL
ADH
Invalid
X, 00 Data Invalid Data
PC + 2 Next OpCode
ADL
ADH
Invalid
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.6
2.6.1
Peripheral Interface
Chip Bus Timing
The internal bus timing is described below for the CPU (or DMAC) writing to and reading from a peripheral (see Figure 2-23.) * The address (AB[15:0]) is output from the CPU on P2. * The data bus (DB[7:0]) is driven by the CPU during a write, or by a peripheral during a read, on P1. * The R/W signal is high for a read and low for a write, and changes on P2. * The EB signal is high when a read or write is not valid, and is low for a valid read or write. It changes on P2. * A PDnB signal (peripheral decode) is assigned to each peripheral and is low when reading from or writing to the peripheral. Each PDnB signal is clocked on P2 timing. The address, R/W, EB, and PDnB signals are latched at the peripheral block on P1, so they must all be valid before this time. The data bus is latched by the CPU during a read, or by a peripheral during a write, on P2; so the value on the data bus must be valid before this time.
2* P1 P2 AB[15:0], R/W, EB, PDnB [P2] AB[15:0], R/W, EB, PDnB latched @ peripheral [P1] AB[2:0], R/W, EB, PDnB peripheral [P1] DB[7:0] [P1] DB[7:0] latched [P2] Figure 2-23. M37640 Internal Bus Timing
Peripheral Interface
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2.6.2
Peripheral Interface and Access Timing
The M37640 offers a wide variety of peripherals. These include RAM, EPROM, UARTs, SIOs, 8-bit and 16-bit timers, various I/O ports, clock generators, and USB core. The interface between the CPU, the peripheral decode block, and peripheral blocks is shown in Figure 2-24. Signals DB7 to DB0, AB2 to AB0, R/W, EB, and at least one peripheral decode (PDnB) are routed to each peripheral. The address signals and peripheral decode signal are used in the peripheral block to create decode signals for each register. Because three address bits are available at the peripheral, a maximum of eight decode signals can be created for each peripheral decode signal. If the peripheral contains more than eight registers, additional peripheral decode signals are routed to the peripheral.
RDbuf [P1] DB[7:0] perDB[7:0]
CPU
P2
[P2]
P1
PD1 R/W E P2 R/W E D1
P2
[AB2:0] Reg decode AB PD1 D1 D2 DN
WRreg
AB[2:0], R/W, EB AB[15:0] Peripheral PD1B PD2B Decode
P1 R/W P1
. .
D1 E R/W
RDreg
. . . . . . .
Register 1 Register 2 Register N Peripheral 1 Peripheral 2 Peripheral N
PDNB
Figure 2-24. Internal Peripheral Interface
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Peripheral Interface
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
The bus timing for reading from and writing to a peripheral is shown in Figure 2-25. * When P2 goes high, the address, R/W, and EB are output from the CPU. All address signals are routed to the peripheral decode block where a peripheral decode signal is generated asynchronously. Also, data read from a peripheral in the previous half cycle is latched in the CPU, and data written to a peripheral in the previous half cycle is latched in the desired register of the peripheral at this time. * When P1 goes high, address AB[2:0], R/W, EB, and PDnB are latched at the peripherals. From these signals, the determination of which peripheral and register inside of that peripheral is to be written or read is made. Also, if the CPU is writing to a peripheral, it begins to drive the data bus at this time with the data to be written to the peripheral. If the CPU is reading from a peripheral, the peripheral begins to drive the data bus as soon as the decode is finished and the data is available from the register. This timing does not apply for the RAM, EPROM, or USB core.
2* P1 P2 CPU: AB, R/W, EB Active Peripheral Decode (PDnB) AB, R/W, EB, PDnB latched @peripheral [P1] AB, R/W, EB, PDnB peripheral READ from peripheral RDbuf RDreg perDB DB CPU read of DB [P2] WRITE to peripheral WRreg[P2] perDB DB
Figure 2-25. M37640 Peripheral Bus Timing
Peripheral Interface
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2.7
Input and Output Ports
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001216 Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P3 direction register Port control register Port P2 pull-up Control Register Description Acronym and Value at Reset P0=00 P0D=00 P1=00 P1D=00 P2=00 P2D=00 P3=00 P3D=00 PTC=00 PUP2=00 Address 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 Port P6 Port P6 direction register Port P5 Port P5 direction register Port P4 Port P4 direction register Port P7 Port P7 direction register Port P8 Port P8 direction register Description Acronym and Value at Reset P6=00 P6D=00 P5=00 P5D=00 P4=00 P4D=00 P7=00 P7D=00 P8=00 P8D=00
Port
Bit 40 Bit 43 Bit 44 Bit 50 Bit 51 Bit 52 Bit 53 Bit 54 Bit 55 Bit 56 Bit 57 Bit 70 Bit 71 Bit 72 Bit 73 Bit 74 multiplexed with EDMA
2nd Function
Bits 41-42 multiplexed with external interrupts INT0, INT1 multiplexed with Timer X CNTR0 pin multiplexed with Timer Y CNTR1 pin multiplexed with XCin multiplexed with Timer 1/2 pulse output pin or XCout multiplexed with OBF0 output to master CPU multiplexed with IBF0 output to master CPU multiplexed with S0 input from master CPU multiplexed with A0 input from master CPU multiplexed with R (E) input from master CPU multiplexed with W (R/W) input from master CPU multiplexed with SOF multiplexed with HOLD multiplexed with S1 input from master CPU multiplexed with IBF1 or HLDA multiplexed with OBF1 input from master CPU
Bits 60-67 multiplexed with Master CPU Bus I/F DQ0-DQ7 pins
Bits 80-83 multiplexed with the first alternate function UART2 pins or 2nd alternate function SIO pins Bits 84-87 multiplexed with the UART1 pins
2.7.1
Ports
This device has 66 programmable I/O pins arranged as ports P00 to P87. Each port bit can be configured as input or output. To set the I/O port bit direction, write a "1" to the corresponding direction register bit to select output mode, or write a "0" to the direction register bit to select input mode.
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Input and Output Ports
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
At reset, all of the direction registers are initialized to 0016, setting all of the I/O ports to input mode. If data is written to a pin and then read from that pin while it is in output mode, the data read is the value of the port latch rather than the value of the pin itself. Therefore, if an external load changes the value of an output pin, the intended output value will still be read correctly. Pins set to input mode are floating (provided that the pull up resistors are not being used) to ensure that the value input to such a pin can be read accurately. In the case when data is written to a pin configured as an input, the data is written only to the port latch; the pin itself remains floating. Most of the I/O Ports are multiplexed with secondary functions. When a GPI/O is multiplexed with a second function, the control signal from the peripheral overrides the direction register. The multiplexing is briefly described below. The second function signals to and from the I/O ports are described in detail in their respective block's description. 2.7.1.1 I/O Ports
Ports 0, 1, and 3 Ports 0 and 1 act as the address bus (AB0-AB15) in Microprocessor and Memory Expansion modes. Bits 0 and 3-7 of Port 3 acts as control signals in Microprocessor and Memory Expansion modes.
Direction Register
Data Bus
Port Latch
Figure 2-26. Port P0, P1, and P3 Block Diagram
Port 2 Port 2 is an 8-bit general purpose I/O port when in single chip mode. In this mode, the port has key-on wake up circuitry which can be used to restart the chip externally from a WIT or STP low power mode. This port also acts as the data bus during microprocessor and memory expansion modes. Port 2 input level can be set to reduced VIHL level or CMOS level by bit 6 of the port control register (PTC).
Pull-up Control
Direction Register
Data Bus
Port Latch
Key-on Wake-up Input
Figure 2-27. Port P2 Block Diagram
Input and Output Ports
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Port 4 Port 4 is a 5-bit general purpose I/O port that can be configured to access special second functions. The port can be set up in any configuration in all three processor modes. Port 40 This pin is multiplexed with the EDMA (Extended Data Memory Access) function. When the MCU is in memory expansion or microprocessor mode and CPMB4 is set to "1", this pin operates as the EDMA output as described in section 2.5.7 on page 2-23.
CPMB4 Direction Register
Data Bus
Port Latch
EDMA Signal
Figure 2-28. Port P40 Block Diagram
Port 41- 42 These pins are multiplexed with external interrupts 0 and 1 (INT0 and INT1). The external interrupt function is enabled by setting the bits to "1" in the interrupt control register that correspond to INT0 and INT1. The interrupt polarity register can be configured to define INT0 and INT1 as active high or low interrupts. See section 2.8.1 on page 2-43 for more information on configuring interrupts.
Direction Register
Data Bus
Port Latch
Interrupt Input
Figure 2-29. Port P41 and P42 Block Diagram
Port 43- 44 These pins are multiplexed with Timer X and Y functions for pin 43 and pin 44 respectively. The timer functions of the pins are independently defined by configuring the timer peripheral. Pin 43 acts as Timer X input pin for pulse width measurement mode and event counter mode or as Timer X output pin for pulse output mode. Pin 43 can also be used as an external interrupt (CNTR0) when Timer X in not in output mode. The polarity is selected in the Timer X mode register. The external interrupt function is enabled by setting the bit to "1" in the interrupt control register that
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Input and Output Ports
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
corresponds to CNTR0. See section 2.8.1 on page 2-43 for more information on configuring interrupts. Pin 44 acts as Timer Y input pin for pulse period measurement mode, pulse H-L measurement mode, and event counter mode or as Timer Y output pin for pulse output mode. Pin 43 can also be used as an external interrupt (CNTR1) when Timer Y in not in output mode. The polarity is selected in the Timer Y mode register. The external interrupt function is enabled by setting the bit to "1" in the interrupt control register that corresponds to CNTR1. See section 2.8.1 on page 2-43 for more information on configuring interrupts.
Timer Counter Input Enable Pulse Output Mode Enable
Direction Register
Data Bus
Port Latch
Timer X, Y Output CNTR0, 1 Input
Figure 2-30. Port P43 and P44 Block Diagram
Port 5 Port 5 is an 8-bit general purpose I/O port that can be configured to access special second functions. The port can be set up in any configuration in all three processor modes. Port 50 This pin is multiplexed with the XCin clock input. When the XCin clock is activated, the pin's I/O is disabled.
CPMA4 Direction Register
Data Bus
Port Latch
CPMA4
CPMA4
XCin Input
Figure 2-31. Port P50 Block Diagram
Input and Output Ports
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Mitsubishi Microcomputers
Port 51 This pin is multiplexed with the XCout clock output and the Timer 1/2 pulse output. When the XCin clock is activated, the pin's I/O is disabled. If XCin is not being used as a system clock or XCout oscillation is disabled, the pin can be configured as the Timer 1/2 pulse output pin. This feature is configured in the Timer123 mode register as described in section 2.13.3 on page 2-87.
Tout Enable Bit
Direction Register
Data Bus
Port Latch
Timer 1/2 Output
Figure 2-32. Port P51 Block Diagram
Port 52- 57 These pins are multiplexed with control pins for the bus interface control block. Pin 52 acts as OBF0 output to a master cpu when DBBC00 is "1".
DBBC00
Direction Register
Data Bus
Port Latch
OBF0
Figure 2-33. Port P52 Block Diagram
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Input and Output Ports
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Pin 53 acts as IBF0 output to a master cpu when DBBC01 is "1".
DBBC01
Direction Register
Data Bus
Port Latch
IBF0
Figure 2-34. Port P53 Block Diagram
Pins 54-57 act as input control signals from a master cpu when DBBC06 is "1". Table 2-2 shows the bus interface control signal that corresponds to each pin.
DBBC06
Direction Register
Data Bus
Port Latch
DBBC06
see table for function
Figure 2-35. Port P54 ~ P57 Block Diagram Table 2-2. Port P54 ~ P57 function Pin 54 55 56 57 Function S0 A0 R(E) W(R/W)
Port 6 Port 6 is an 8-bit general purpose I/O port that can be configured to access special second functions. The port acts as the data bus interface for the bus interface control block when DBBC06 is "1". The port can be set up in any configuration in all three processor modes.
Input and Output Ports
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MBI Write S0 S1 MBI Read
Direction Register
Data Bus
Port Latch
Output Buffer 1 A0 Status Register 1
S0 MBI Read
S1 MBI Read
Output Buffer 1 A0 Status Register 1
S0 MBI Write S1 MBI Write
Input Buffer 0 Input Buffer 1
Figure 2-36. Port P6 Block Diagram
Port 7 Port 7 is a 5-bit general purpose I/O port that can be configured to access special second functions. Port 70 This pin is multiplexed with the USB start of frame pulse (SOF) output. When USBC6 is a "1", this pin outputs the USB SOF.
USBC6
Direction Register
Data Bus
Port Latch
SOF
Figure 2-37. Port P70 Block Diagram
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Port 71 This pin is multiplexed with the HOLD function. When the MCU is in memory expansion or microprocessor mode and CPMB5 is set to "1", this pin operates as the HOLD input as described in section 2.5.6 on page 2-23.
CPMB5
Direction Register
Data Bus
Port Latch
CPMB5
HOLD
Figure 2-38. Port P71 Block Diagram
Port 72 This pin is multiplexed with the S1 input control signal from a master cpu. When DBBC17 is "1", the pin takes on the function of the S1 input control signal.
DBBC17
Direction Register
Data Bus
Port Latch
DBBC17
S1
Figure 2-39. Port P72 Block Diagram
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Mitsubishi Microcomputers
Port 73 This pin is multiplexed with the IBF1 output control signal for a master cpu and the HLDA function. When DBBC11 and DBBC17 are "1", the pin takes on the function of the IBF1 output control signal. When the MCU is in memory expansion or microprocessor mode, CPMB5 is set to "1", and the IBF1 function is not enabled, this pin operates as the HLDA output as described in section 2.5.6 on page 2-23.
DBBC11 DBBC17 CPMB5
Direction Register
Data Bus
Port Latch
IBF1 HLDA
Figure 2-40. Port P73 Block Diagram
Port 74 This pin is multiplexed with the OBF1 control pin for the bus interface control block. Pin 74 acts as OBF1 output to a master cpu when DBBC10 and DBBC17 are "1".
DBBC10 DBBC17
Direction Register
Data Bus
Port Latch
OBF1
Figure 2-41. Port P74 Block Diagram
Port 8 Port 8 is an 8-bit general purpose I/O port that can be configured to access special second functions. The port can be set up in any configuration in all three processor modes.
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Port 80 This pin is multiplexed with the SIO SRDY signal and the UART2 TxD signal. When UART2 is in transmit mode, the pin acts as the TxD output signal. When the pin is not being used as the UART2 TxD output and bit 4 of the SIO control register 1 (SIOCON1) is a "1", the port acts as the SIO SRDY output signal. If during this function, the SIO is configured in slave mode, this pin acts as a slave input from a master. See section 2.15.2 on page 2-102 for more SIO information.
SRDY Output Selection Bit UART2 Transmit Control Bit SIO Slave mode selection bit
Direction Register
Data Bus
Port Latch
SIO Ready Output UART2 TxD Output
SIO slave control
SIO Slave mode selection bit
Figure 2-42. Port P80 Block Diagram
Port 81 This pin is multiplexed with the SIO SCLK signal and the UART2 RxD signal. When UART2 is in receive mode, the pin acts as the RxD input signal. When the pin is not being used as the UART2 RxD input and bit 2 of the SIO control register 1 (SIOCON1) is a "1", the port acts as the SIO SCLK signal. In this mode a "1" in bit 6 of SIOCON1 configures the pin to output SCLK whereas a "0" configures the pin to input SCLK.
SIO Clock Selection Bit SIO Port Selection Bit UART2 receive control bit UART2 receive control Bit
Direction Register
Data Bus
Port Latch
SIO Clock Selection Bit
SIO Clock Output
UART2 RxD input SIO clock input
UART2 receive control bit
Figure 2-43. Port P81 Block Diagram
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Mitsubishi Microcomputers
Port 82 This pin is multiplexed with the SIO SRxD signal and the UART2 CTS signal. When bit 5 of the UART2 control register (U2CON) is a "1", the port acts as the CTS input signal. When the pin is not being used as the UART2 CTS input and bit 2 of the SIO control register 2 (SIOCON2) is a "1", the port acts as the SIO SRxD input signal.
SIO Receive Enable Bit UART2 CTS Enable Bit
Direction Register
Data Bus
Port Latch
UART2 CTS Enable Bit
UART2 CTS input SIO RxD input
Figure 2-44. Port P82 Block Diagram
Port 83 This pin is multiplexed with the SIO STxD signal and the UART2 RTS signal. When bit 6 of the UART2 control register (U2CON) is a "1", the port acts as the RTS output signal. When the pin is not being used as the UART2 RTS output and bit 3 of the SIO control register 1 (SIOCON1) is a "1", the port acts as the SIO STxD output signal.
P-Channel Output Disable Bit Transmit Complete Signal SIO Port Selection Bit
UART2 RTS Enable Bit
Direction Register
Data Bus
Port Latch
SIO TxD Output UART2 RTS Output
Figure 2-45. Port P83 Block Diagram
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Port 84 This pin is multiplexed with the UART1 TxD signal. When UART1 is in transmit mode, the pin acts as the TxD output signal.
UART1 Transmit Control Bit
Direction Register
Data Bus
Port Latch
UART1 TxD Output
Figure 2-46. Port P84 Block Diagram
Port 85 This pin is multiplexed with the UART1 RxD signal. When UART1 is in receive mode, the pin acts as the RxD input signal.
UART1 receive control Bit
Direction Register
Data Bus
Port Latch
UART1 RxD input
Figure 2-47. Port P85 Block Diagram
Port 86 This pin is multiplexed with the UART1 CTS signal. When bit 5 of the UART1 control register (U1CON) is a "1", the port acts as the CTS input signal.
UART1 CTS Enable Bit
Direction Register
Data Bus
Port Latch
UART1 CTS input
Figure 2-48. Port P86 Block Diagram
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7600 Series M37640E8-XXXF Preliminary Specification Port 87
Mitsubishi Microcomputers
This pin is multiplexed with the UART1 RTS signal. When bit 6 of the UART1 control register (U1CON) is a "1", the port acts as the RTS output signal.
UART1 RTS Enable Bit
Direction Register
Data Bus
Port Latch
UART1 RTS Output
Figure 2-49. Port P87 Block Diagram
2.7.1.2
Power and Ground Pins
There are two Vss and two Vdd pins that supply power to the MCU. There is also one analog Vdd (AVdd) and one analog Vss (AVss) pin for the analog circuits. 2.7.1.3 CNVss Pin
The level of the signal input to the CNVss pin at reset determines whether the chip enters single chip or microprocessor mode. With CNVss connected to Vdd, the MCU enters microprocessor mode after a reset. After the reset sequence has been completed, the mode can be changed by modifying the value of bits 0 and 1 of CPMA. However, while CNVss is connected Vdd, bit 1 of CPMA can not be overwritten. With CNVss connected to Vss, the MCU enters single chip mode after a reset. 2.7.1.4 Xin and Xout Pins
The Xin and Xout pins are clock input and output pins. This device has a built-in clock generation circuit whose oscillation frequency is set by a quartz oscillator. Also, an external clock source can be used by connecting the Xin pin to a clock generator and leaving the Xout pin floating. The frequency of Xin can be 48MHz with an external clock source and 24MHz with a crystal. 2.7.1.5 XCin and XCout Pins
The P50/XCin and P51/Tout/XCout pins are clock input and output pins. This device has a built-in clock generation circuit whose oscillation frequency is set by a ceramic or quartz oscillator. An external clock may also be used by connecting the XCin pin to a clock generator and leaving the XCout pin floating. The frequency of XCin can be 5MHz with an external clock source or 32KHz with a crystal. 2.7.1.6 RESET Pin
The MCU is reset by holding RESET low for at least 2s before returning to high.
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Mitsubishi Microcomputer 2.7.1.7 RDY Pin
7600 Series M37640E8-XXXF Preliminary Specification
The P30/RDY pin is used to control the slow memory wait function of the MCU. For a detailed description of this pin, see section 2.5.5 on page 2-19. 2.7.1.8 DMAout Pin
When the chip is in microprocessor or memory expansion mode, the DMAout (P33/DMAout) pin goes high during a DMA transfer. 2.7.1.9 out Pin
When the MCU is in microprocessor or memory expansion mode, pin P34 outputs the internal system clock out. When the STP or WIT instructions are executed, the output of the out pin stops at a high level. 2.7.1.10 SYNCout Pin
When the MCU is in microprocessor or memory expansion mode, the SYNCout pin outputs a signal that is high for one-half cycle of out every time an OpCode is fetched. 2.7.1.11 RD and WR Pins
When the MCU is in microprocessor or memory expansion mode, a read control signal is output from the RD pin and write control signal is output from the WR pin (P36/WR and P37/RD). A low output from the RD pin indicates that the CPU is reading and a low output from the WR pin indicates that the CPU is writing. These signals are active for both internal and external accesses. 2.7.1.12 LPF Pin
When the Frequency Synthesizer is active, the LPF pin is the loop filter for the Frequency Synthesizer. 2.7.1.13 USB D+/D- Pins
These two pins are used as the data transmission/reception lines for the USB core. 2.7.1.14 Ext. Cap Pin
When the USB transceiver voltage converter is used, an external capacitor must be connected to this pin.
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2.7.2
Port Control Register
This device is equipped with a port control register to turn on and off the slew rate control and to control the input levels for port 2 and the MBI pins. (see Figure 2-50.).
MSB 7 PTC7 PTC6 PTC0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 LSB 0 Address: 001016 Access: R/W Reset: 0016
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
Slew Rate Control Bit Ports 0-3 (bit 0) 0: Disabled 1: Enabled Slew Rate Control Bit Port 4 (bit 1) 0: Disabled 1: Enabled Slew Rate Control Bit Port 5 (bit 2) 0: Disabled 1: Enabled Slew Rate Control Bit Port 6 (bit 3) 0: Disabled 1: Enabled Slew Rate Control Bit Port 7 (bit 4) 0: Disabled 1: Enabled Slew Rate Control Bit Port 8 (bit 5) 0: Disabled 1: Enabled Port 2 Input Level Select Bit (bit 6) 0: Reduced VIHL level input 1: CMOS level input Master Bus Input Level Select Bit (bit 7) 0: CMOS level input 1: TTL level input
Figure 2-50. Port Control Register
2.7.3
Port 2 Pull-up Control Register
This device is equipped with internal pull-ups on Port 2 that can be enabled by software. Each bit of the pull-up control register controls a corresponding pin of Port 2. The pull-up control register pulls up the port when the port is in input mode. The value of the pull-up control register has no effect when the port is in output mode.
MSB 7 PUP27 PUP26 PUP20 PUP21 PUP22 PUP23 PUP24 PUP25 PUP26 PUP27 PUP25 PUP24 PUP23 PUP22 PUP21 PUP20 LSB 0 Address: 001216 Access: R/W Reset: 0016
Pull-up Control for Port 2 (bit 0) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 1) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 2) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 3) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 4) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 5) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 6) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 7) 0: Disabled 1: Enabled
Figure 2-51. Pull-up Control Register
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7600 Series M37640E8-XXXF Preliminary Specification
2.8
Interrupt Control Unit
Description Acronym and Value at Reset IREQB=00 IREQC=00 ICONA=00 Address 000616 000716 001116 Description Interrupt control register B Interrupt control register C Interrupt polarity selection register Acronym and Value at Reset ICONB=00 ICONC=00 IPOL=00
Address 000216 000316 000416 000516
Interrupt request register A IREQA=00 Interrupt request register B Interrupt request register C Interrupt control register A
The interrupt control unit (ICU), a specialized peripheral, is described in detail in this section. This series supports a maximum of 23 maskable interrupts, one software interrupt, and one reset vector that is treated as a non-maskable interrupt. See Table 2-3 for the interrupt sources, jump destination addresses, interrupt priorities, and section references for the interrupt request sources.
2.8.1
Interrupt Control
Each maskable interrupt has associated with it an interrupt request bit and an interrupt enable bit. These bits, along with the I flag, determine whether interrupt events can cause an interrupt service request to be generated. An interrupt request bit is set to at "1" when its corresponding interrupt event is activated. The bit is cleared to a "0" when the interrupt is serviced or when a "0" is written to the bit. The bit can not be set high by writing "1" to it. Each interrupt enable bit determines whether the interrupt request bit it is paired with is seen when the interrupts are polled. When the interrupt enable bit is a "0", the interrupt request bit is not seen; and when the enable bit is a "1", the interrupt request is seen. The interrupt request register configurations for the 23 maskable interrupts are shown in Figure 2-52., Figure 2-53., and Figure 2-54. The interrupt control register configurations for the 23 maskable interrupts are shown in Figure 2-55., Figure 2-56., and Figure 2-57.
MSB 7 LSB 0 Address: 000216 Access: R/W Reset: 0016
IRA7
IRA6 IRA0 IRA1 IRA2 IRA3 IRA4 IRA5 IRA6 IRA7
IRA5
IRA4
IRA3
IRA2
IRA1
IRA0
USB Function Interrupt Request (bit 0) USB SOF Interrupt Request (bit 1) External Interrupt 0 Request (bit 2) External Interrupt 1 Request (bit 3) DMAC channel 0 Interrupt Request (bit 4) DMAC channel 1 Interrupt Request (bit 5) UART1 Receive Buffer Full Interrupt Request (bit 6) UART1 Transmit Interrupt Request (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 2-52. IREQA Configuration
Interrupt Control Unit
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MSB 7
IRB7
IRB6 IRB0 IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7
IRB5
IRB4
IRB3
IRB2
IRB1
IRB0
LSB 0
Address: 000316 Access: R/W Reset: 0016
UART1 Error Sum Interrupt Request (bit 0) UART2 Receive Buffer Full Interrupt Request (bit 1) UART2 Transmit Interrupt Request (bit 2) UART2 Error Sum Interrupt Request (bit 3) Timer X Interrupt Request (bit 4) Timer Y Interrupt Request (bit 5) Timer 1 Interrupt Request (bit 6) Timer 2 Interrupt Request (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 2-53. IREQB Configuration
MSB Reserved 7
IRC6 IRC0 IRC1 IRC2 IRC3 IRC4 IRC5 IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
LSB 0
Address: 000416 Access: R/W Reset: 0016
Timer 3 Interrupt Request (bit 0) External CNTR0 Interrupt Request (bit 1) External CNTR1 Interrupt Request (bit 2) SIO Interrupt Request (bit 3) Input Buffer Full Interrupt Request (bit 4) Output Buffer Empty Interrupt Request (bit 5) Key-on Wake-up Interrupt Request (bit 6) 0: No interrupt request issued 1: Interrupt request issued
Bit 7
Reserved (Read/Write "0")
Figure 2-54. IREQC Configuration
MSB 7
ICA7
ICA6 ICA0 ICA1 ICA2 ICA3 ICA4 ICA5 ICA6 ICA7
ICA5
ICA4
ICA3
ICA2
ICA1
ICA0
LSB 0
Address: 000516 Access: R/W Reset: 0016
USB Function Interrupt Enable (bit 0) USB SOF Interrupt Enable (bit 1) External Interrupt 0 Enable (bit 2) External Interrupt 1 Enable (bit 3) DMAC channel 0 Interrupt Enable (bit 4) DMAC channel 1 Interrupt Enable (bit 5) UART1 Receive Buffer Full Interrupt Enable (bit 6) UART1 Transmit Interrupt Enable (bit 7) 0: Interrupt Disable 1: Interrupt Enable
Figure 2-55. ICONA Configuration
MSB 7
ICB7
ICB6 ICC0 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7
ICB5
ICB4
ICB3
ICB2
ICB1
ICB0
LSB 0
Address: 000616 Access: R/W Reset: 0016
UART1 Error Sum Interrupt Enable (bit 0) UART2 Receive Buffer Full Interrupt Enable (bit 1) UART2 Transmit Interrupt Enable (bit 2) UART2 Error Sum Interrupt Enable (bit 3) Timer X Interrupt Enable (bit 4) Timer Y Interrupt Enable (bit 5) Timer 1 Interrupt Enable (bit 6) Timer 2 Interrupt Enable (bit 7) 0: Interrupt Disable 1: Interrupt Enable
Figure 2-56. ICONB Configuration
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Address: 000716 Access: R/W Reset: 0016
MSB 7
Reserved
ICC6 ICC0 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6
ICC5
ICC4
ICC3
ICC2
ICC1
ICC0
LSB 0
Timer 3 Interrupt Enable (bit 0) External CNTR0 Interrupt Enable (bit 1) External CNTR1 Interrupt Enable (bit 2) SIO Interrupt Enable (bit 3) Input Buffer Full Interrupt Enable (bit 4) Output Buffer Empty Interrupt Enable (bit 5) Key-on Wake-up Interrupt Enable (bit 6) 0: Interrupt disabled 1: Interrupt enabled
Bit 7
Reserved (Read/Write "0")
Figure 2-57. ICONC Configuration
The interrupt polarity register allows the user to select the external interrupt edge which triggers the interrupt request. The configuration of the polarity register for the external interrupts is shown in Figure 2-58.
MSB 7 Reserved Reserved INT0 Pol Reserved Reserved Reserved Reserved INT1 Pol INT0 Pol LSB 0 Address: 001116 Access: R/W Reset: 0016
INT1 Pol
Bits 2-7
INT0 Interrupt Edge Selection Bit 0: Falling edge selected. 1: Rising edge selected. INT1 Interrupt Edge Selection Bit 0: Falling edge selected. 1: Rising edge selected. Reserved (Read/Write "0")
Figure 2-58. IPOL Configuration
Interrupt Control Unit
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7600 Series M37640E8-XXXF Preliminary Specification
Table 2-3 Interrupt Vector Table Jump Destination Storage Address (Vector Address) High-order Byte FFFF FFFD FFFB FFF9 FFF7 FFF5 FFF3 FFF1 FFEF FFED FFEB FFE9 FFE7 FFE5 FFE3 FFE1 FFDF FFDD FFDB FFD9 FFD7 FFD5 FFD3 FFD1 FFCF FFCD FFCB Low-order Byte FFFE FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC FFEA FFE8 FFE6 FFE4 FFE2 FFE0 FFDE FFDC FFDA FFD8 FFD6 FFD4 FFD2 FFD0 FFCE FFCC FFCA Reserved for factory use Reserved for factory use User Reset (Non-Maskable) USB Function Interrupt USB SOF Interrupt External Interrupt 0 External Interrupt 1 DMAC Channel 0 Interrupt DMAC Channel 1 Interrupt UART1 Receiver Buffer Full UART1 Transmit Interrupt UART1 Error Sum Interrupt UART2 Receiver Buffer Full UART2 Transmit Interrupt UART2 Error Sum Interrupt Timer X Interrupt Timer Y Interrupt Timer 1 Interrupt Timer 2 Interrupt Timer 3 Interrupt External CNTR0 Interrupt External CNTR1 Interrupt SIO Interrupt Input Buffer Full Interrupt Output Buffer Empty Interrupt Key-on Wake Up
Mitsubishi Microcomputers
Remarks Reference
Priority Interrupt
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
RSRV1 RSRV2 Reset USB SOF INT0 INT1 DMA1 DMA2 U1RBF U1TX U1ES U2RBF U2TX U2ES TX TY T1 T2 T3 CNTR0 CNTR1 SIO IBF OBE KEY BRK
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6
LSB IREQA and ICONA MSB LSB IREQB and ICONB MSB LSB IREQC and ICONC MSB
Section 2.9.2.1 Section 2.9.2.2 Section 2.8.1 Section 2.8.1 Section 2.11 Section 2.11 Section 2.14.7 Section 2.14.7 Section 2.14.7 Section 2.14.7 Section 2.14.7 Section 2.14.7 Section 2.13 Section 2.13 Section 2.13 Section 2.13 Section 2.13 Section 2.13.1.6 Section 2.13.2 Section 2.15 Section 2.10 Section 2.10 Section 2.18 Corresponding Register Assignment
BRK Instruction (Non-Maskable)
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
2.8.2
Interrupt Sequence and Timing
The interrupts are polled prior to the beginning of each instruction. An interrupt service request is generated when an interrupt event has its interrupt request bit set to a "1", its interrupt enable bit is set to a "1", and the interrupt inhibit flag I is set low. The I flag is used to disable all maskable interrupts. When this bit is set to a "1", only a BRK instruction or a user Reset can cause an interrupt service request to be generated. Figure 2-59 is a simplified version of the logic that controls whether an interrupt service request is generated.
Interrupt Request Bit Interrupt Enable Bit
Interrupt Inhibit Flag I Interrupt Request BRK Instruction Reset
Figure 2-59. Interrupt Service Request Control Logic
The time elapsed from the occurrence of an interrupt event until execution of its service routine varies from 7 cycles to 23 cycles, depending on what instruction is executing when the interrupt event occurs (see Figure 2-60.)
Interrupt Request 23 to 7 Cycles (1.92 s to 0.583 s, when f() = 12 MHz) Interrupt Processing Routine 2 cycles, dummy cycles for pipeline postprocessing 5 cycles, stack push and vector fetch
Current Instruction Maximum 16 cycles * Minimum 0 cycles * For DIV Instruction
Figure 2-60. Execution Time Prior to Interrupt Service Routine
When an interrupt service request occurs, the current instruction stream is temporarily halted and the appropriate interrupt service routine is executed. After the interrupt service routine ends, the current instruction stream is resumed with the next instruction. The interrupt service request causes the MCU to automatically push the high-order byte of the program counter, the low-order byte of the program counter, and the contents of the processor status register onto the stack. A push consists of storing data at the stack address and decrementing the stack pointer by one as illustrated in Figure 2-2. The I flag is set to a "1" to prevent other interrupts from being serviced during the interrupt service routine, and the request bit corresponding to the interrupting event is automatically cleared to "0". The program counter is set to the address specified in the vector table for the interrupt being serviced. This address contains the address for the first instruction of the interrupt service routine. The timing for the pushing of data onto the stack, and fetching the starting address of the interrupt routine is illustrated in Figure 2-61.
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out P1 P2 SYNCout RD WR Address Data
PC PC S,CPMA2 S-1,CPMA2 S-2,CPMA2 (Int Vector)L (Int Vector)H ADL,ADH
Invalid
Invalid
PCH
PCL
PS
ADL
ADH
Next OpCode
Figure 2-61. Interrupt Cycle Timing
See Figure 2-62. for the stack and program counter modifications that occur when an interrupt request is serviced.
Program Counter PCL PCH Program Counter (L) Program Counter (H) Stack Pointer S (S) Interrupt Accept Stack (in Zero/One Page) Program Counter PCL PCH S Loaded values of the vector address corresponding to the accepted interrupt. Stack Pointer (S) - 3 Interrupt Disable (S) - 3 Processor Status Register Program Counter (L) Program Counter (H) (S) Interrupt Enable (S) Stack (in Zero/One Page)
Figure 2-62. Stack Pointer and Program Counter Modifications During Interrupt Service Sequence
Returning from an interrupt is accomplished by executing an RTI instruction. This causes the MCU to pop the contents of the process status register and the low-order and high-order bytes of the program counter from the stack. The I flag is cleared to "0" when the process status value is restored from the stack.
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7600 Series M37640E8-XXXF Preliminary Specification
2.9
Address 001316 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916
Universal Serial Bus
Description USB Control Register USB Address Register USB Power Management Register USB Interrupt Status Register 1 USB Interrupt Status Register 2 USB Interrupt Enable Register 1 USB Interrupt Enable Register 2 USB Frame Number Low Register USB Endpoint Index USB Endpoint x IN CSR Acronym and Value at Reset USBC=00 USBA=00 USBPM=00 USBIS1=00 USBIS2=00 USBIE1=FF USBIE2=33 USBSOFL=00 USBINDEX=00 IN_CSR=00 Address 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 Description USB Endpoint x OUT CSR USB Endpoint x IN MAXP USB Endpoint x OUT MAXP USB Endpoint x OUT WRT CNT Low USB Endpoint x OUT WRT CNT High Reserved USB Endpoint 0 FIFO USB Endpoint 1 FIFO USB Endpoint 2 FIFO USB Endpoint 3 FIFO USB Endpoint 4 FIFO USBFIFO0=N/A USBFIFO1=N/A USBFIFO2=N/A USBFIFO3=N/A USBFIFO4=N/A Acronym and Value at Reset OUT_CSR=00 IN_MAXP OUT_MAXP WRT_CNTL=00 WRT_CNTH=00
USB Frame Number High Register USBSOFH=00
The Universal Serial Bus (USB) has the following features: * Complete USB Specification (version 1.0) Compatibility * Error Handling capabilities * FIFOs: * Endpoint 0: IN 16-byte * Endpoint 1: IN 512-byte * Endpoint 2: IN 32-byte * Endpoint 3: IN 16-byte * Endpoint 4: IN 16-byte * Five independent IN and five * Complete Device Configuration * Supports All Device Commands * Supports Full-Speed Functions * Support of All USB Transfer Types: * Isochronous * Bulk * Control * Interrupt * Suspend/Resume Operation * On-chip USB Transceiver with voltage converter * Start-of-frame interrupt and output pin OUT 16-byte OUT 800-byte OUT 32-byte OUT 16-byte OUT 16-byte independent OUT endpoints
Universal Serial Bus
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2.9.1
USB Function Control Unit (USB FCU)
The implementation of the USB by this device is accomplished chiefly through the device's USB Function Control Unit. The Function Control Unit's overall purpose is to handle the USB packet protocol layer. The Function Control Unit notifies the MCU that a valid token has been received. When this occurs, the data portion of the token is routed to the appropriate FIFO. The MCU transfers the data to, or from, the host by interacting with that endpoint's FIFO and CSR register. (see Figure 2-63.) The USB Function Control Unit is composed of five sections: * Serial Interface Engine (SIE) * Generic Function Interface (GFI) * Serial Engine Interface Unit (SIU) * Microcontroller Interface (MCI) * USB Transceiver 2.9.1.1 Serial Interface Engine
The SIE interfaces to the USB serial data and handles Deserialization/Serialization of data, NRZI encoding decoding, Clock extraction, CRC generation and checking, Bit Stuffing, and other specifications pertaining to the USB protocol such as handling inter-packet time-outs and PID decoding. 2.9.1.2 Generic Function Interface
The GFI handles the all USB standard requests from the host through the control endpoint (endpoint zero), handles Bulk, Isochronous and Interrupt transfers through endpoints 1-4. The GFI handles read pointer reversal for re-transmit the current data set; write pointer reversal for re-receive the last data set; data toggle synchronization. 2.9.1.3 Serial Engine Interface Unit
The SIU block decodes the Address and Endpoint fields from the USB host. 2.9.1.4 Microcontroller Interface Unit
The MCI block handles the Microcontroller interface and performs address decoding and synchronization of control signals. 2.9.1.5 USB Transceiver
The USB transceiver, designed to interface with the physical layer of the USB, is compliant with the USB Specification (version 1.0) for high speed devices. It consists of two 6-ohm drivers, a receiver, and schmitt triggers for single-ended receive signals. The transceiver also includes a voltage converter. The voltage converter can supply 3.0 - 3.6V to the transmitter when the rest of the chip (CPU, USB FCU, etc...) operates at 4.15 - 5.25V. To enable the voltage converter, set bit 4 of the USB Control Register (USBC) to a "1". To disable the voltage converter, set bit 4 of the USBC to a "0". Refer to section 4.5 "USB Transceiver" for more detailed information.
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
SIU D+ CPU MCI SIE Transceiver
D-
GFI
FIFOs
Figure 2-63. USB Function Control Unit Block Diagram
2.9.2
USB Interrupts
There are two types of USB interrupts in this device: the first type is the USB function (including overrun/underrun, reset, suspend and resume) interrupt, used to control the flow of data and USB power control; the second type is start-of-frame (SOF) interrupt, used to monitor the transfer of isochronous (ISO) data. 2.9.2.1 USB Function Interrupt
Endpoint 1-4, each has two interrupt status bits associated with it to control the data transfer or to report a STALL/UNDER_RUN/OVER_RUN condition. The EPx_OUT_INT bit is set when the USB FCU successfully receives a packet of data, or sets the FORCE_STALL bit, or the OVER_RUN bit of the Endpoint x OUT CSR. The EPx_IN_INT bit is set when the USB FCU successfully sends a packet of data, or sets the UNDER_RUN bit of the Endpoint x IN CSR. Endpoint 0 - the control endpoint has one interrupt status bit associated with it to control the data transfer or report a STALL condition. The EP0_INT is set when the USB FCU successfully receives/sends a packet of data, or sets the SETUP_END bit, the FORCE_STALL bit, or clears the DATA_END bit in the Endpoint 0 IN CSR. Each endpoint interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable Register 1 and 2. The USB Interrupt Status Register 1 and 2 are used to indicate pending interrupts for a given endpoint. The USB FCU sets the interrupt status bits. The CPU writes a "1" to clear the corresponding status bit. By writing back the same value it read, the CPU will clear all the existing interrupts. The CPU must read then write both status registers, writing status register 1 first and status register 2 second to guarantee proper operation. The suspend interrupt status bit is set if a USB suspend signaling is received. If the device is in suspend mode, the resume interrupt status bit is set when a USB resume signaling is received. There is a single interrupt enable bit for both of suspend and resume interrupts (bit 7 of the interrupt enable register 2). The USB reset interrupt status bit is set if a USB reset signaling is received. When this bit is set, all USB internal registers will be reset to their default values except this bit itself. This bit is cleared by the CPU writing a "0" to it. When the CPU detects a USB reset interrupt, it needs to re-initialize the USB block in order to accept packets from the host.
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The Over/Underrun status bit is set (applicable to endpoints used for isochronous data transfer), when an overrun condition occurs in an endpoint (CPU is too slow to unload the data from the FIFO), or when an underrun condition occurs in an endpoint (CPU is too slow to load the data to the FIFO). The USB Function Interrupt (sum of all individual function interrupts) is enabled by setting the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit. 2.9.2.2 USB SOF Interrupt
The USB SOF (Start-Of-Frame) interrupt is used to control the transfer of isochronous data. The USB FCU generates a start-of-frame interrupt when a start-of-frame packet is received. The USB SOF interrupt is enabled by setting the corresponding bit in the Interrupt Control Register of the Interrupt Control Unit.
2.9.3
USB Endpoint FIFOs
The USB FCU has an IN (transmit) FIFO and an OUT (receive) FIFO for each endpoint. Both FIFOs support up to two separate data sets of variable size (except Endpoint 0), and provide the ability of back-to-back transmission and reception. Throughout this specification, the terms "IN FIFO" and "OUT FIFO" refer these FIFOs associated with the current endpoint as specified by the Endpoint Index Register. In the event of a bad transmission/reception, the USB FCU handles all the read/write pointer reversal and data set management tasks when it is applicable. 2.9.3.1 IN (Transmit) FIFOs
The CPU/DMA writes data to the endpoint's IN FIFO location specified by the FIFO write pointer, which automatically increments by "1" after a write. The CPU/DMA should only write data to the IN FIFO if the IN_PKT_RDY bit of the IN CSR is a "0". Endpoint 0 IN FIFO Operation: The CPU writes a "1" to the IN_PKT_RDY bit after it finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet is successfully transmitted to the host (ACK is received from the host) or the SETUP_END bit of the IN CSR is set to a "1". Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of IN CSR) = "0": MAXP > half of the IN FIFO size: The CPU writes a "1" to IN_PKT_RDY bit after the CPU/DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit after the packet is successfully transmitted to the host (ACK is received from the host). MAXP <= half of the IN FIFO size: The CPU writes a "1" to the IN_PKT_RDY bit after the CPU/ DMAC finishes writing a packet of data to the IN FIFO. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready to accept another data packet (The FIFO can hold up to two data packets at the same time in this configuration, for back-to-back transmission). Since the set and the clear operations could be as fast as 83ns (one 12MHz clock period) apart from each other, the set may be transparent to the user. Endpoint 1-4 IN FIFO Operation when AUTO_SET (bit 7 of IN CSR) = "1": MAXP > half of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size) is written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit to a `1' automatically. The USB FCU clears the IN_PKT_RDY bit after the packet is successfully transmitted to the host (ACK is received from the host).
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MAXP <= half of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum packet size) is written to the IN FIFO by the CPU/DMAC, the USB FCU sets the IN_PKT_RDY bit to a `1' automatically. The USB FCU clears the IN_PKT_RDY bit as soon as the IN FIFO is ready to accept another data packet (The FIFO can hold up to two data packets at the same time in this configuration, for back-to-back transmission). Since the set and the clear operations could be as fast as 83ns (one 12MHz clock period) apart from each other, the set may be transparent to the user. A software or a hardware flush acts as if a packet is being successfully transmitted out to the host. If there is one packet in the IN FIFO, a flush will cause the IN FIFO to be empty, if there are two packets in the IN FIFO, a flush will cause the older packet to be flushed out from the IN FIFO. Flush will update the IN FIFO status (IN_PKT_RDY and TX_NOT_EMPTY bits). The status of the endpoint 1-4 IN FIFO for both of the above cases, could be obtained from the IN CSR as follows:
IN_PKT_RDY 0 0 1 1 TX_NOT_EMPTY 0 1 0 1 TX FIFO Status No data packet in TX FIFO One data packet in TX FIFO if MAXP <= half of the FIFO size. Invalid Two data packets in TX FIFO if MAXP <= half of the FIFO size or One data packet in TX FIFO if MAXP > half of the FIFO size
Interrupt Endpoints: Any endpoint can be used for interrupt transfers. For normal interrupt transfers, the interrupt transactions behave the same as bulk transactions, i.e., no special setting is required. The IN endpoints may also be used to communicate rate feedback information for certain types of isochronous functions. This is done by setting the INTPT bit in the IN CSR register of the corresponding endpoint. When the INTPT bit is set, the data toggle bits will be changed after each packet is sent to the host without regard to the presence or type of handshake packet. The following outlines the operation sequence for an IN endpoint used to communicate rate feedback information: 1. Set MAXP > 1/2 of the endpoint's FIFO size; 2. Set INTPT bit of the IN CSR; 3. Flush the old data in the FIFO; 4. Load interrupt status information and set IN_PKT_RDY bit in the IN CSR; 5. Repeat steps 3 & 4 for all subsequent interrupt status updates. 2.9.3.2 Out (Receive) FIFOs
The USB FCU writes data to the endpoint's OUT FIFO location specified by the FIFO write pointer, which automatically increments by one after a write. When the USB FCU has successfully received a data packet, it sets the OUT_PKT_RDY bit to a "1" in the OUT CSR. The CPU/DMAC should only read data from the OUT FIFO if the OUT_PKT_RDY bit of the OUT CSR is a "1", with the exception of endpoint 1 (see detail description below). Endpoint 0 OUT FIFO Operation: The USB FCU sets the OUT_PKT_RDY bit to a `1' after it has successfully received a packet of data from the host. The CPU writes a "0" to the OUT_PKT_RDY bit after the packet of data is unloaded from the OUT FIFO by the CPU. Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of OUT CSR) = "0":
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MAXP > half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a "1" after it has successfully received a packet of data from the host. The CPU writes a "0" to the OUT_PKT_RDY bit after the packet of data is unloaded from the OUT FIFO by the CPU/DMAC. MAXP <= half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a "1" after it has successfully received a packet of data from the host. The CPU writes a "0" to the OUT_PKT_RDY bit after the packet of data is unloaded from the OUT FIFO by the CPU/DMAC. In this configuration, the FIFO can hold upto two data packets at the same time, for back-to-back reception. Therefore, the OUT_PKT_RDY bit may remain set after the CPU writes a "0" to it if there is another packet in the OUT FIFO. Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of OUT CSR) = "1": MAXP > half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a "1" after it has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a `0' automatically when the number of bytes of data equal to the MAXP (maximum packet size) is unloaded from the OUT FIFO by the CPU/DMAC. MAXP <= half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a "1" after it has successfully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a "0" automatically when the number of bytes of data equal to the MAXP (maximum packet size) is unloaded from the OUT FIFO by the CPU/DMAC. In this configuration, the FIFO can hold up to two data packets at the same time, for back-to-back reception. Therefore, the OUT_PKT_RDY bit may remain set after one packet (size equal to MAXP) of data is unloaded if there is another packet in the OUT FIFO. A software flush acts as if a packet is being unloaded from the OUT FIFO. If there is one packet in the OUT FIFO, a flush will cause the OUT FIFO to be empty, if there are two packets in the OUT FIFO, a flush will cause the older packet to be flushed out from the OUT FIFO. Special case for OUT endpoint 1: In addition to the OUT FIFO operations described above, the DMAC can also start unloading the OUT FIFO as soon as there is data in it (byte-by-byte transfer). This feature should only be used with ISO transfers. See section 2.11 "Direct Memory Access Controller" on page 2-69 for details.
2.9.4
USB Special Function Registers
The MCU controls USB operation through the use of special function registers (SFR). This section describes in detail each USB related SFR. Certain USB SFRs are endpoint-indexed: the Control & Status Registers (IN CSR and OUT CSR), the Maximum Packet Size Registers (IN MAXP and OUT MAXP), and the Write Count Registers (OUT WRT CNT). To access each endpoint-indexed SFR, the target endpoint number should be written to the Endpoint Index Register first. The lower 3 bits (EPINDX2:0) of the Endpoint Index Register are used for endpoint selection. Note: Each endpoint's FIFO Register is NOT endpoint-indexed.
Some USB special function registers have a mix of read/write, read only, and write only register bits. Additionally, the bits may be configured to allow the user to write only a "0" or a "1" to individual bits. When accessing these registers, writing a "0" to a register that can only be set to a "1" by the CPU will have no affect on that register bit. Each figure and description of the special function registers will detail this operation. The USB Control Register, shown in Figure 2-64, is used to control the USB FCU. This register is not reset by a USB reset signaling. After the USB is enabled (USBC7 set to "1"), a minimum delay of 250 ns (three 12Mhz clock periods) is needed before performing any other USB register read/write operations.
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MSB 7
USBC7
USBC6 Bit 0 USBC1
USBC5
USBC4
USBC3
Reserved
USBC1
Reserved
LSB 0
Address: 001316 Access: R/W Reset: 0016
Reserved (Read/Write "0") USB Default State Selection Bit (bit 1) 0: In default state after powerup/reset 1: In default state after received the USB reset signaling Reserved (Read/Write "0") Transceiver Voltage Converter High/Low Current Mode Selection Bit (bit 3) 0: High current mode 1: Low current mode USB Transceiver Voltage Converter Enable Bit (bit 4) 0: USB transceiver voltage converter disabled 1: USB transceiver voltage converter enabled USB Clock Enable Bit (bit 5) 0: 48 MHz clock to the USB block is disabled. 1: 48 MHz clock to the USB block is enabled. USB SOF Port Select Bit (bit 6) 0: USB SOF output is disabled. P70 is used as GPIO pin. 1: USB SOF output is enabled USB Enable Bit (bit 7) 0: USB block is disabled, all USB internal registers are held at their default values. 1: USB block is enabled
Bit 2 USBC3
USBC4
USBC5
USBC6
USBC7
Figure 2-64. USB Control Register
The USB Function Address Register, shown in Figure 2-65, maintains the 7-bit USB address assigned by the host. The USB FCU uses this register value to decode USB token packet addresses. At reset, when the device is not yet configured, the value is 0016.
MSB 7 Reserved FUNAD6 FUNAD6:0 Bit 7 FUNAD5 FUNAD4 FUNAD3 FUNAD2 FUNAD1 FUNAD0 LSB 0 Address: 005016 Access: R/W Reset: 0016
7-bit programmable Function Address (bits 6-0) Reserved (Read/Write "0")
Figure 2-65. USB Function Address Register
The USB Power Management Register, shown in Figure 2-66, is used for power management in the USB FCU. USB Suspend Detection Flag When the USB FCU receives a USB suspend signaling, it sets the SUSPEND bit and generates an interrupt. The CPU writes a "0" to clear this bit when the device is resumed by the host (resume interrupt is generated and Resume Detection Flag is set) or remote wake-up by itself (The CPU writes a "1" to Remote Wake-up Bit). USB Resume Detection Flag When the USB FCU is in suspend mode and receives a USB resume signaling, it sets the RESUME bit, and generates an interrupt. The CPU writes a "0" to clear this bit. USB Remote Wake-up Bit The CPU writes a "1" to the WAKEUP bit for remote wake-up. While this bit is set, and the USB FCU is in suspend mode, it will generate a resume signaling to the host. The CPU must keep this bit set for a minimum of 10ms and a maximum of 15ms before writing a "0" to this bit.
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MSB 7
Reserved
Reserved SUSPEND
Reserved
Reserved
Reserved
WAKEUP
RESUME SUSPEND LSB 0
Address: 005116 Access: R/W Reset: 0016
RESUME
WAKEUP
USB Suspend Detection Flag (bit 0) (Write "0" only or Read) 0: No USB suspend signal detected 1: USB suspend signal detected USB Resume Detection Flag (bit 1) (Write "0" only or Read) 0: No USB resume signal detected 1: USB resume signal detected USB Remote Wake-up Bit (bit 2) 0: End remote resume signaling 1: Remote resume signaling (If SUSPEND = "1") Reserved (Read/Write "0")
Bit7:3
Figure 2-66. USB Power Management Register
The USB FCU is able to generate a USB function interrupt as discussed in section 2.9.2.1. The USB Interrupt Status Registers, shown in Figure 2-67 and Figure 2-68, are used to indicate the condition that caused a USB function interrupt to the CPU. A "1" indicates the corresponding condition caused a USB function interrupt. The USB Interrupt Status Registers can be cleared by writing back to the register the same value that was read. To ensure proper operation, the CPU should read both USB interrupt status registers, then write back the same values it read to these two registers for clearing the status bits. The CPU must write the USB Interrupt Status Register 1 first, then the USB Interrupt Status Register 2. The registers cannot be cleared by writing a "0" to the bits that are a "1". The USB Interrupt Enable Registers, shown in Figure 2-69 and Figure 2-70, are used to enable the corresponding interrupt status conditions, which can generate a USB function interrupt. If the bit to a corresponding interrupt condition is "0", that condition will not generate a USB function interrupt. If the bit is a "1", that condition can generate a USB function interrupt. Upon reset, all USB interrupt status conditions are enabled except bit 7 of USB Interrupt Enable Register 2 - i.e., suspend and resume interrupt is disabled.
MSB 7 INTST7 INTST6 INTST0 Bit 1 INTST2 INTST3 INTST4 INTST5 INTST6 INTST7 INTST5 INTST4 INTST3 INTST2 Reserved INTST0 LSB 0 Address: 005216 Access: R/W Reset: 0016
USB Endpoint 0 Interrupt Status Flag (bit 0) Reserved (Read/Write "0") USB Endpoint 1 IN Interrupt Status Flag (bit 2) USB Endpoint 1 OUT Interrupt Status Flag (bit 3) USB Endpoint 2 IN Interrupt Status Flag (bit 4) USB Endpoint 2 OUT Interrupt Status Flag (bit 5) USB Endpoint 3 IN Interrupt Status Flag (bit 6) USB Endpoint 3 OUT Interrupt Status Flag (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 2-67. USB Interrupt Status Register 1
INTST0 is set to a "1" by the USB FCU if (in Endpoint 0 IN CSR): * Successfully receives a packet of data * Successfully sends a packet of data * IN0CSR3 (DATA_END) bit is cleared * IN0CSR4 (FORCE_STALL) bit is set * IN0CSR5 (SETUP_END) bit is set INTST2, INTST4, INTST6 or INTST8 is set to a "1" by the USB FCU if (in Endpoint x IN CSR): * Successfully sends a packet of data * INXCSR1 (UNDER_RUN) bit is set
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INTST3, INTST5, INTST7 or INTST9 is set to a "1" by the USB FCU if (in Endpoint xOUT CSR): * Successfully receives a packet of data * OUTXCSR1 (OVER_RUN) bit is set * OUTXCSR4 (FORCE_STALL) bit is set
MSB 7 INTST15 INTST14 INTST8 INTST9 Bit 3:2 INTST12 INTST13 INTST14 INTST15 INTST13 INTST12 Reserved Reserved INTST9 INTST8 LSB 0 Address: 005316 Access: R/W Reset: 0016
USB Endpoint 4 In Interrupt Status Flag (bit 0) USB Endpoint 4 Out Interrupt Status Flag (bit 1) Reserved (Read/Write "0") USB Overrun/Underrun Interrupt Status Flag (bit 4) USB Reset Interrupt Status Flag (bit 5) USB Resume Signaling Interrupt Status Flag (bit 6) USB Suspend Signaling Interrupt Status Flag (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 2-68. USB Interrupt Status Register 2
INTST12 is set to a "1" by the USB FCU if an overrun or underrun condition occurs in any of the endpoints. INTST13 is set to a "1" by the USB FCU if a USB reset signaling from the host is received. All USB internal registers will be reset to their default values except this bit. INTST14 is set to a "1" by the USB FCU if a USB resume signaling is received from the host. INTST15 is set to a "1" by the USB FCU if a USB suspend signaling is received from the host.
MSB 7 INTEN7 INTEN6 INTEN0 Bit 1 INTEN2 INTEN3 INTEN4 INTEN5 INTEN6 INTEN7 INTEN5 INTEN4 INTEN3 INTEN2 Reserved INTEN0 LSB 0 Address: 005416 Access: R/W Reset: FF16
USB Endpoint 0 In Interrupt Enable Bit (bit 0) Reserved (Read/Write "0") USB Endpoint 1 IN Interrupt Enable Bit (bit 2) USB Endpoint 1 OUT Interrupt Enable Bit (bit 3) USB Endpoint 2 IN Interrupt Enable Bit (bit 4) USB Endpoint 2 OUT Interrupt Enable Bit (bit 5) USB Endpoint 3 IN Interrupt Enable Bit (bit 6) USB Endpoint 3 OUT Interrupt Enable Bit (bit 7) 0: Interrupt disabled 1: Interrupt enabled
Figure 2-69. USB Interrupt Enable Register 1
MSB 7
INTEN15
Reserved INTEN8 INTEN9 Bit 3:2 INTEN12 INTEN13 Bit 6 INTEN15
INTEN13
INTEN12
Reserved
Reserved
INTEN9
INTEN8
LSB 0
Address: 005516 Access: R/W Reset: 3316
USB Endpoint 4 IN Interrupt Enable Bit (bit 0) USB Endpoint 4 OUT Interrupt Enable Bit (bit 1) Reserved (Read/Write "0") USB Overrun/Underrun Interrupt Enable Bit (bit 4) USB Reset Interrupt Enable Bit (bit 5) Reserved (Read/Write "0") USB Suspend/Resume Signaling Interrupt Enable Bit (bit 7) 0: Interrupt disabled 1: Interrupt enabled
Figure 2-70. USB Interrupt Enable Register 2
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The USB Frame Number Low Register, shown in Figure 2-71, contains the lower 8 bits of the 11-bit frame number received from the host. The USB Frame Number High Register, shown in Figure 2-72 contains the upper 3 bits of the 11-bit frame number received from the host.
MSB 7 FN7 FN6 FN7:0 FN5 FN4 FN3 FN2 FN1 FN0 LSB 0 Address: 005616 Access: R Reset: 0016
Lower 8 bits of the 11-bit frame number issued with a SOF token
Figure 2-71. USB Frame Number Low Register
MSB 7
Reserved
Reserved FN10:8 Bits 7:3
Reserved
Reserved
Reserved
FN10
FN9
FN8
LSB 0
Address: 005716 Access: R Reset: 0016
Upper 3 bits of the 11-bit frame number issued with a SOF token Reserved (Read "0")
Figure 2-72. USB Frame Number High Register
The USB Endpoint Index Register, shown in Figure 2-73, identifies the endpoint pair. It serves as an index to endpoint-specific IN CSR, OUT CSR, IN MAXP, OUT MAXP and OUT WRT CNT registers. This register also contains two global bits, ISO_UPD and AUTO_FL for endpoints 1-4 regarding the isochronous data transfer. If ISO_UPD = "0", a data packet in an endpoint's IN FIFO is always `ready to transmit' upon receiving the next IN_TOKEN from the host (with matched address & endpoint number). If ISO_UPD = "1" and the ISO bit of the corresponding endpoint's IN CSR is set, then the internal `ready to transmit' signal to the transmit control logic is delayed until the next SOF. In this way the data loaded in frame n will be transmitted out in frame n+1. The ISO_UPD bit is a global bit for endpoints 1 to 4, and works with isochronous pipes only. If AUTO_FL = "1", ISO_UPD = "1", and a particular IN endpoint's ISO bit is set, then at the time the USB FCU detects a SOF packet, if the corresponding IN endpoint's IN_PKT_RDY = "1", the USB FCU automatically flushes the oldest packet from the IN FIFO. In this case, IN_PKT_RDY = "1" indicates that two data packet are in the IN FIFO. Since, for ISO transfer, double buffering is a requirement, MAXP must set to be less than or equal to 1/2 of the FIFO size.
MSB 7
ISO_UPD AUTO_FL EPINDX2:0
Reserved
Reserved
Reserved Bit 0 0: 1: 0: 1: 0:
EPINDX2 EPINDX1 EPINDX0 LSB 0
Address: 005816 Access: R/W Reset: 0016
Endpoint Index: Bit 2 Bit 1 0 0 0 0 0 1 0 1 1 0 Others:
Function Endpoint 0 Function Endpoint 1 Function Endpoint 2 Function Endpoint 3 Function Endpoint 4 Undefined
Bits 3:5 AUTO_FL
Reserved (Read/Write "0") AUTO_FLUSH Bit (bit 6) 0: Hardware auto FIFO flush disabled 1: Hardware auto FIFO flush enabled ISO_UPDATE Bit (bit 7) 0: ISO_UPDATE disabled 1: ISO_UPDATE enabled
ISO_UPD
Figure 2-73. USB Endpoint Index Register
The Endpoint 0 IN CSR (Control & Status Register), shown in Figure 2-74, contains the control and status information of Endpoint 0. 2-58 7/9/98 Universal Serial Bus
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IN0CSR0 (OUT_PKT_RDY): The USB FCU sets this bit to a "1" upon receiving a valid SETUP/OUT token from the host. The CPU clears this bit after unloading the FIFO, by way of writing a "1" to IN0CSR6. The CPU should not clear the OUT_PKT_RDY bit before finishes decoding the host request. If IN0CSR2 (SEND_STALL) needs to be set - the CPU decodes an invalid or unsupported request - the setting IN0CSR6 = "1" & IN0CSR2 = "1" should be done in a same CPU write. IN0CSR1 (IN_PKT_RDY): The CPU writes a "1" to this bit after finishes writing a packet of data to the endpoint 0 FIFO. The USB FCU clears this bit after the packet is successful transmitted to the host, or the IN0CSR5 (SETUP_END) bit is set. IN0CSR2 (SEND_STALL): The CPU writes a "1" to this bit if it decodes an invalid or unsupported standard device request from the host. The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during control transfer data or status stages) while this bit is set. The CPU writes a "0" to clear this bit. IN0CSR3 (DATA_END): For control transfers, the CPU writes a "1" to this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of data from/to the FIFO. This bit indicates to the USB FCU that the specific amount of data in the setup phase is transferred. The USB FCU will advance to the status phase once this bit is set. When the status phase completes, the USB FCU clears this bit. When this bit is set to a "1", and the host again requests or sends more data, the USB FCU will return a STALL handshake. IN0CSR4 (FORCE_STALL): The USB FCU sets this bit to a "1" if the host sends out a larger data packet than the MAXP size, or if during a data stage a command pipe is sent more data or is requested to return more data than was indicated in the setup stage (also see description for IN0CSR3). The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during data or status stages) while this bit is set. The CPU writes a "0" to clear this bit. IN0CSR5 (SETUP_END): The USB FCU sets this bit to a "1" if a control transfer has ended before the specific length of data is transferred during the data phase. The CPU clears this bit by way of writing a "1" to IN0CSR7. Once the CPU sees the SETUP_END bit set, it should stop accessing the FIFO to service the previous setup transaction. If OUT_PKT_RDY is set at the same time SETUP_END is set, it indicates the previous setup transaction ended, and a new SETUP token is in the FIFO. IN0CSR6 and IN0CSR7: These bits are used to clear IN0CSR0 and IN0CSR5 respectively. Writing a "1" to these bits will clear the corresponding register bit.
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MSB 7
IN0CSR7
IN0CSR6 IN0CSR0
IN0CSR5
IN0CSR4
IN0CSR3
IN0CSR2
IN0CSR1
IN0CSR0
LSB 0
Address: 005916 Access: R/W Reset: 0016
IN0CSR1
IN0CSR2
IN0CSR3
IN0CSR4
IN0CSR5
IN0CSR6
IN0CSR7
OUT_PKT_RDY Flag (bit 0) (Read Only - Write "0") 0: Out packet is not ready 1: Out packet is ready IN_PKT_RDY Bit (bit 1) (Write "1" only or Read) 0: In packet is not ready 1: In packet is ready SEND_STALL Bit (bit 2) (Write "1" only or Read) 0: No action 1: Stall Endpoint 0 by the CPU DATA_END Bit (bit 3) (Write "1" only or Read) 0: No action 1: Last packet of data transferred from/to the FIFO FORCE_STALL Flag (bit 4) (Write "0" only or Read) 0: No action 1: Stall Endpoint 0 by the USB FCU SETUP_END Flag (bit 5) (Read Only - Write "0") 0: No action 1: Control transfer ended before the specific length of data is transferred during the data phase SERVICED_OUT_PKT_RDY Bit (bit 6) (Write Only - Read "0") 0: No change 1: Clear the OUT_PKT_RDY bit (IN0CSR0) SERVICED_SETUP_END Bit (bit 7) (Write Only - Read "0") 0: No change 1: Clear the STUP_END bit (IN0CSR5)
Figure 2-74. USB Endpoint 0 IN CSR
The USB Endpoint x IN CSR ((Control & Status Register), shown in Figure 2-75, contains control and status information of the respective IN endpoint 1-4. The specific endpoint is selected by the USB Endpoint Index Register. INXCSR0 (IN_PKT_RDY) and INXCSR5 (TX_FIFO_NOT_EMPTY): These two bits are read together to determine IN FIFO status. A "1" can be written to the INXCSR0 bit by the CPU to indicate a packet of data is written to the FIFO (See Chapter 2.9.3.1. IN (Transmit) FIFOs for detail). INXCSR1 (UNDER_RUN) This bit is used in ISO mode only to indicate to the CPU that a FIFO underrun has occurred. The USB FCU sets this bit to a "1" at the beginning of an IN token if no data packet is in the FIFO. Setting this bit will cause the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear this bit. INXCSR2 (SEND_STALL): The CPU writes a "1" to this bit when the endpoint is stalled (transmitter halt). The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. INXCSR3 (ISO): The CPU writes a "1" to this bit to initialize the respective endpoint as an isochronous endpoint for IN transactions. INXCSR4 (INTPT): The CPU writes a "1" to this bit to initialize this endpoint as a status change endpoint for IN transactions. This bit is set only if the corresponding endpoint is to be used to communicate rate feedback information (see Chapter 2.9.3.1. IN (Transmit) FIFOs for details). INXCSR5 (TX_FIFO_NOT_EMPTY): The USB FCU sets this bit to a "1" when there is data in the IN FIFO. This bit in conjunction with IN_PKT_RDY bit will provide the transmit FIFO status information (see Chapter 2.9.3.1. IN (Transmit) FIFOs for details). INXCSR6 (FLUSH): The CPU writes a "1" to this bit to flush the IN FIFO. If there is one packet in the IN FIFO, a flush will cause the IN FIFO to be empty, if there are two packets in the IN FIFO, a flush will cause the older packet to be flushed out from the IN FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredictable results.
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INXCSR7 (AUTO_SET): If the CPU sets this bit to a "1", the IN_PKT_RDY bit is set automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see Chapter 2.9.3.1. IN (Transmit) FIFOs for details).
MSB 7 INXCSR7 INXCSR6 INXCSR5 INXCSR4 INXCSR3 INXCSR2 INXCSR1 INXCSR0 LSB 0 INXCSR0 IN_PKT_RDY Bit (bit 0) (Write "1" only or Read) 0: In packet is not ready 1: In packet is ready UNDER_RUN Flag (bit 1) (Write "0" only or Read) 0: No FIFO underrun 1: FIFO underrun has occurred SEND_STALL Bit (bit 2) 0: No action 1: Stall IN Endpoint X by the CPU ISO Bit (bit 3) 0: Select non-isochronous transfer 1: Select isochronous transfer INTPT Bit (bit 4) 0: Select non-rate feedback interrupt transfer 1: Select rate feedback interrupt transfer TX_NOT_EPT Flag (bit 5) (Read Only - Write "0") 0: Transmit FIFO is empty 1: Transmit FIFO is not empty FLUSH Bit (bit 6) (Write Only - Read "0") 0: No action 1: Flush the FIFO AUTO_SET Bit (bit 7) 0: AUTO_SET disabled 1: AUTO_SET enabled Address: 005916 Access: R/W Reset: 0016
INXCSR1
INXCSR2
INXCSR3
INXCSR4
INXCSR5
INXCSR6
INXCSR7
Figure 2-75. USB Endpoints x IN CSR
All bits in USB Endpoint 0 OUT CSR (Control & Status Register), shown in Figure 2-76, are reserved (all control and status info is in Endpoint 0 IN CSR)
MSB 7 Reserved Reserved Bits 7:0 Reserved Reserved Reserved Reserved Reserved Reserved LSB 0 Address: 005A16 Access: R Reset: 0016
Reserved (Read "0")
Figure 2-76. USB Endpoint 0 OUT CSR
The USB Endpoint x OUT CSR (Control & Status Register), shown in Figure 2-77, contains control and status information of the respective OUT endpoint 1-4. The specific endpoint is selected by the USB Endpoint Index Register. OUTXCSR0 (OUT_PKT_RDY): The USB FCU sets the this bit to a "1" after it successfully receives a packet of data from the host. This bit is cleared by the CPU or by the USB FCU after a packet of data is unloaded from the FIFO (See Chapter 2.9.3.2. Out (Receive) FIFOs for details). OUTXCSR1 (OVER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets this bit to a "1" at the beginning of an OUT token if the OUTXCSR0 (OUT_PKT_RDY) bit is not cleared. Setting this bit will cause the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a "0" to clear this bit. OUTXCSR2 (SEND_STALL): The CPU writes a "1" to this bit when the endpoint is stalled (receiver halt). The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. OUTXCSR3 (ISO): The CPU sets this bit to a "1" to initialize the respective endpoint as an Isochronous endpoint for OUT transactions.
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OUTXCSR4 (FORCE_STALL): The USB FCU sets this bit to a "1" if the host sends out a larger data packet than the MAXP size. The USB FCU returns a STALL handshake while this bit is set. The CPU writes a "0" to clear this bit. OUTXCSR5 (DATA_ERR): The USB FCU sets this bit to a "1" to indicate a CRC error or a bit stuffing error received in an ISO packet. The CPU writes a "0" to clear this bit. OUTXCSR6 (FLUSH): The CPU writes a "1" to this to flush the OUT FIFO. If there is one packet in the OUT FIFO, a flush will cause the OUT FIFO to be empty, if there are two packets in the OUT FIFO, a flush will cause the older packet to be flushed out from the OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce unpredictable results. OUTXCSR7 (AUTO_CLR): If the CPU sets this bit to a "1", the OUT_PKT_RDY bit is cleared automatically by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see Chapter 2.9.3.2. Out (Receive) FIFOs for details).
MSB 7
OUTXCSR7 OUTXCSR6 OUTXCSR5 OUTXCSR4 OUTXCSR3 OUTXCSR2 OUTXCSR1 OUTXCSR0 LSB
Address: 005A16 Access: R/W Reset: 0016
0
OUTXCSR0
OUTXCSR1
OUTXCSR2
OUTXCSR3
OUTXCSR4
OUTXCSR5
OUTXCSR6
OUTXCSR7
OUT_PKT_RDY Flag (bit 0) (Write "0" only or Read) 0: Out packet is not ready 1: Out packet is ready OVER_RUN Flag (bit 1) (Write "0" only or Read) 0: No FIFO overrun 1: FIFO overrun occurred SEND_STALL Bit (bit 2) 0: No action 1: Stall OUT Endpoint X by the CPU ISO Bit (bit 3) 0: Select non-isochronous transfer 1: Select isochronous transfer FORCE_STALL Flag (bit 4) (Write "0" only or Read) 0: No action 1: Stall Endpoint X by the USB FCU DATA_ERR Flag (bit 5) (Write "0" only or Read) 0: No error 1: CRC or bit stuffing error received in an ISO packet FLUSH Bit (bit 6) (Write Only - Read "0") 0: No action 1: Flush the FIFO AUTO_CLR Bit (bit 7) 0: AUTO_CLR disabled 1: AUTO_CLR enabled
Figure 2-77. USB Endpoint x OUT CSR
The USB Endpoint x IN MAXP, shown in Figure 2-78, indicates the maximum packet size (MAXP) of an Endpoint x IN packet. The default value for Endpoint 0 is 8 bytes, the default values for Endpoints 1-4 are 0 bytes. The CPU can change this value, as negotiated with the host controller through the SET_DESCRIPTOR command.
MSB 7 IMAXP7 IMAXP6 IMAXP7:0 IMAXP5 IMAXP4 IMAXP3 IMAXP2 IMAXP1 IMAXP0 LSB 0 Address: 005B16 Access: R/W
Maximum packet size (MAXP) of Endpoint x IN packet. MAXP = n for endpoints 0, 2, 3, 4 MAXP = n * 8 for endpoint 1 n is the value written to this register. For endpoints that support a smaller FIFO size, unused bits are not implemented (always write "0" to those bits)
Figure 2-78. USB Endpoint x IN MAXP
The USB Endpoint x OUT MAXP, shown in Figure 2-79, indicates the maximum packet size (MAXP) of an Endpoint x OUT packet. The default values for endpoints 1-4 are 0 bytes. The CPU can change this value, as negotiated with the host controller through the SET_DESCRIPTOR command. For endpoint 0, all bits in this register are reserved: Endpoint 0 uses IN MAXP register for both IN and OUT transfers. 2-62 7/9/98 Universal Serial Bus
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MSB 7
OMAXP7
OMAXP6 OMAXP7:0
OMAXP5
OMAXP4
OMAXP3
OMAXP2
OMAXP1
OMAXP0 LSB 0
Address: 005C16 Access: R/W
Maximum packet size (MAXP) of Endpoint x OUT packet. MAXP = n for endpoints 2, 3, 4 MAXP = n * 8 for endpoint 1 n is the value written to this register. For endpoints that support a smaller FIFO size, unused bits are not implemented (always write "0" to those bits)
Figure 2-79. USB Endpoint x OUT MAXP
The USB Endpoint x OUT WRT CNT Low & the USB Endpoint x OUT WRT CNT High registers, shown in Figure 2-80 and Figure 2-81, contain the number of bytes in the Endpoint x OUT FIFO. The USB FCU sets the values in these two Write Count Registers after having successfully received a packet of data from the host. The CPU reads these two registers to determine the number of bytes to be read from the FIFO. The CPU should read WRT CNT Low first then WRT CNT High.
MSB 7 W_CNT7 W_CNT6 W_CNT7:0 W_CNT5 W_CNT4 W_CNT3 W_CNT2 W_CNT1 W_CNT0 LSB 0 Address: 005D16 Access: R Reset: 0016
Byte Count. This register contains the lower 8 bits of the byte count register
Figure 2-80. USB Endpoint x OUT WRT CNT Low
MSB 7
Reserved
Reserved W_CNT9:8 Bits 7:2
Reserved
Reserved
Reserved
Reserved
W_CNT9
W_CNT8
LSB 0
Address: 005E16 Access: R Reset: 0016
Byte Count. This register contains the upper 2 bits of the byte count register Reserved (Read "0")
Figure 2-81. USB Endpoint x OUT WRT CNT High
The USB Endpoint x FIFO Registers, shown in Figure 2-82 through Figure 2-86, are the USB IN (transmit) and OUT (receive) FIFO data registers. The CPU writes data to these registers for the corresponding Endpoint IN FIFO and reads data from these registers for the corresponding Endpoint OUT FIFO.
MSB 7 DATA_7 DATA_6 DATA_7:0 DATA_5 DATA_4 DATA_3 DATA_2 DATA_1 DATA_0 LSB 0 Address: 006016 Access: R/W Reset: N/A
Endpoint 0 IN/OUT FIFO register
Figure 2-82. USB Endpoint 0 FIFO Register
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006116 Access: R/W Reset: N/A
Endpoint 1 IN/OUT FIFO register
Figure 2-83. USB Endpoint 1 FIFO Register
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006216 Access: R/W Reset: N/A
Endpoint 2 IN/OUT FIFO register
Figure 2-84. USB Endpoint 2 FIFO Register
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MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006316 Access: R/W Reset: N/A
Endpoint 3 IN/OUT FIFO register
Figure 2-85. USB Endpoint 3 FIFO Register
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006416 Access: R/W Reset: N/A
Endpoint 4 IN/OUT FIFO register
Figure 2-86. USB Endpoint 4 FIFO Register
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2.10 Master CPU Bus Interface
Address 004816 004916 004A16 004C16 004D16 004E16 Pin Description Data bus buffer register 0 Data bus buffer status register 0 Data bus buffer register 1 Data bus buffer status register 1 Acronym and Value at Reset DBB0=00 DBBS0=00 DBB1=00 DBBS1=00
Data bus buffer control register 0 DBBC0=00
Data bus buffer control register 1 DBBC1=00 Description Pin P56 P57 P72 P73 P74 Description is multiplexed with R or E is multiplexed with W or R/W is multiplexed with S1 is multiplexed with IBF1 is multiplexed with OBF1
P60-P67 are multiplexed with DQ0-DQ7 P52 P53 P54 P55 is multiplexed with OBF0 is multiplexed with IBF0 is multiplexed with S0 is multiplexed with A0
This device has a bus interface function with 2 I/O buffers that can be operated in slave mode by control signals from the master CPU (see Figure 2-87. Bus Interface Circuit). The bus interface can be connected directly to either a R/W type of CPU or a CPU with RD and WR separate signals. Slave mode is selected with the bit 7 of the data buffer control register 0. The single data bus buffer mode and the double data bus buffer mode are selected with bit 7 of the data bus buffer control register 1. When selecting the double data bus buffer mode, port P72 becomes S1 input. Prior to enabling the MBI, port 6 must be placed in input mode by writing 0016 to P6D (001516).
OBF0 IBF0 A0 S0 R W
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
W R S1 A0 IBF1OBF1
System Bus
Output Data Bus Buffer 1
Data Bus Buffer Control Register 0
Output Data Bus Buffer 0
Data Bus Buffer Control Register 1
Input Data Bus Buffer 1
b7 U7 U6 U5 U4 A00 U2
Input Data Bus Buffer 0
b7 U7 U6 U5 U4 A01 U2 IBF1
OBF1
RD WR DBB0
RD WR DBB1
DBBS0 DBBS1
b1 b0
IBF0
OBF 0
b1 b0
b0
b0
Data Bus
Figure 2-87. Bus Interface Circuit
When data is written to the MCU from the master CPU, an input buffer full interrupt request occurs. Similarly, when data is read from the master CPU, an output buffer empty interrupt request occurs. Master CPU Bus Interface 7/9/98 2-65
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When the bus interface is operating, DQ0-DQ7 become a 3-state data bus that sends and receives data, command, and status to and from the master CPU. At the same time, W, R, S0, S1, and A0 become host CPU control signal input pins. The two input buffer full interrupt requests and two output buffer full requests are multiplexed as shown in Figure 2-88. The bus interface can be operated under normal MCU control or under on-chip DMA control for fast data transfer. If a master CPU has a large amount of data to be transferred, use of the on-chip DMA controller is highly recommended. The bus interface signal input level can be programmed as CMOS level (default) or as TTL level. Bit 7 of the Port Control Register (PTC7) is used for the input level selection.
Input buffer full flag 0 IBF0 Input buffer full flag 1 IBF1 Output buffer full flag 0 OBF0 Output buffer full flag 1 OBF1 IBF0 IBF1 IBF Set interrupt request at this rising edge
Rising Edge detection circuit
One-shot pulse generating circuit
Rising Edge detection circuit
One-shot pulse generating circuit
Input Buffer full interrupt request signal IBF
Rising Edge detection circuit Rising Edge detection circuit
One-shot pulse generating circuit One-shot pulse generating circuit
Output Buffer Empty interrupt request signal OBE
OBF0 (OBE0) OBF1 (OBE1) OBE Set interrupt request at this rising edge
Figure 2-88. Data Bus Buffer Interrupt Request Circuit
MSB 7
DBBS07
DBBS06 DBBS00
DBB05
DBBS04
DBBS03
DBBS02
DBBS01
DBBS00
LSB 0
Address: 004916 Access: R/W Reset: 0016
DBBS01
DBBS02 DBBS03 DBBS04 DBBS05 DBBS06 DBBS07
Output Buffer Full (OBF0) Flag (bit 0) 0: Output buffer empty. 1: Output buffer full. Input Buffer Full (IBF0) Flag (bit 1) 0: Input buffer empty. 1: Input buffer full. User Definable (U2) Flag (bit 2) A0 (A00) Flag (bit 3) Indicates the A0 status when IBF flag is set User Definable (U4) Flag (bit 4) User Definable (U5) Flag (bit 5) User Definable (U6) Flag (bit 6) User Definable (U7) Flag (bit 7)
Figure 2-89. Data Bus Buffer Status Register 0
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MSB 7
DBBC07
DBBC06 DBBC00
Reserved DBBC04
DBBC03
DBBC02
DBBC01
DBBC00
DBBC01
DBBC02
DBBC03
DBBC04
DBBC05 DBBC06
DBBC07
Access: R/W OBF Output Selection Bit (bit 0) Reset: 0016 0: P52 pin is operated as GPIO 1: P52 pin is operated as OBF0 output pin IBF Output Selection Bit (bit 1) 0: P53 pin is operated as GPIO 1: P53 pin is operated as IBF0 output pin IBF0 Interrupt Selection Bit (bit 2) 0: IBF0 interrupt is generated by both write-data (A0 = "0") and write-command (A0 = "1") 1: IBF0 interrupt is generated by write-command (A0 = "1") only Output buffer 0 empty interrupt disable Bit (bit 3) 0: Enabled 1: Disabled Input buffer 0 full interrupt disable Bit (bit 4) 0: Enabled 1: Disabled Reserved (Read/Write "0") Master CPU Bus Interface Enable Bit (bit 6) 0: P60-P67, P54-P57 are GPIO pins 1: P60-P67, P54-P57 are bus interface signals DQ0-DQ7, S0, A0, R, W respectively. Bus Interface Type Selection Bit (bit 7) 0: RD, WR separate type bus 1: R/W type bus.
LSB 0
Address: 004A16
Figure 2-90. Data Bus Buffer Control Register 0
Address: 004D16 Access: R/W Reset: 0016
MSB 7
DBBS17
DBBS16 DBBS10
DBB15
DBBS14
DBBS13
DBBS12
DBBS11
DBBS10
LSB 0
DBBS11
DBBS12 DBBS13 DBBS14 DBBS15 DBBS16 DBBS17
Output Buffer Full (OBF1) Flag (bit 0) 0: Output buffer empty. 1: Output buffer full. Input Buffer Full (IBF1) Flag (bit 1) 0: Input buffer empty. 1: Input buffer full. User Definable (U2) Flag (bit 3) A0 (A01) Flag (bit 2) Indicates the A0 status when IBF flag is set User Definable (U4) Flag (bit 4) User Definable (U5) Flag (bit 5) User Definable (U6) Flag (bit 6) User Definable (U7) Flag (bit 7)
Figure 2-91. Data Bus Buffer Status Register 1
MSB DBBC17 7
Reserved DBBC10
Reserved DBBC14
DBBC11
DBBC12
DBBC13
DBBC14
DBBC15 DBBC16 DBBC17
Access: R/W OBF1 Output Selection Bit (bit 0) Reset: 0016 0: P74 pin is operated as GPIO 1: P74 pin is operated as OBF1 output pin if DBBC17 = "1" IBF1 Output Selection Bit (bit 1) 0: P73 pin is operated as GPIO 1: P73 pin is operated as IBF1 output pin if DBBC17 = "1" IBF1 Interrupt Selection Bit (bit 2) 0: IBF1 interrupt is generated by both write-data (A0 = "0") and write-command (A0 = "1") 1: IBF1 interrupt is generated by write-command (A0 = "1") only Output Buffer 1 Empty interrupt disable Bit (bit 3) 0: Enabled 1: Disabled Input Buffer 1 Full interrupt disable Bit (bit 4) 0: Enabled 1: Disabled Reserved (Read/Write "0") Reserved (Read/Write "0") Data Bus Buffer Function Selection Bit (bit 7) 0: Single data bus buffer - P72 is used as GPIO 1: Double data bus buffer - P72 is used as S1 input
DBBC13
DBBC12
DBBC11
DBBC10
LSB 0
Address: 004E16
Figure 2-92. Data Bus Buffer Control Register 1
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2.10.1 Data Bus Buffer Status Registers (DBBS0, DBBS1)
The data bus buffer status register is an 8-bit register that indicates the data bus status, with bits 0, 1, and 3 being dedicated read-only bits. Bits 2, 4, 5, 6, and 7 are user definable flags set by software, and can be read and write. When the A0 pin is high, the master CPU can read the contents of this register. Output Buffer Full Flag (OBF0, OBF1) The OBF0 and the OBF1 flags are set high when data is written to the output data bus buffer by the slave CPU and is cleared to "0" when data is read by the master CPU. Input Buffer Full Flag (IBF0, IBF1) The IBF0 and the IBF1 flags are set high when data is written to the input data bus buffer by the master CPU and is cleared to "0" when data is read by the slave CPU. A0 Flag (A00, A01) The level of the A0 pin is latched when data has been written from the host CPU to the input data bus buffer.
2.10.2 Input Data Bus Buffer Registers (DBBIN0, DBBIN1)
The data on the data bus is latched into DBBIN0 or DBBIN1 by a write request from the master CPU. The data in DBBIN0 or DBBIN1 can be read from the data bus buffer register in the SFR area.
2.10.3 Output Data Bus Buffer Registers (DBBOUT0, DBBOUT1)
Data is set in DBBOUT0 or DBBOUT1 by writing to the data bus buffer register in the SFR area. When the A0 pin is low, the data of this register is output by a read request from the host CPU.
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2.11 Direct Memory Access Controller
Address 003F16 004016 004116 004216 004316 004416 004516 004616 004716 Description DMAC index and status register DMAC channel x mode register 1 DMAC channel x mode register 2 DMAC channel x source register Low DMAC channel x source register High DMAC channel x destination register Low DMAC channel x destination register High Acronym and Value at Reset DMAIS=00 DMAxM1=00 DMAxM2=00 DMAxSL=00 DMAxSH=00 DMAxDL=00 DMAxDH=00
DMAC channel x transfer count register Low DMAxCL=00 DMAC channel x transfer count register High DMAxCH=00
This device contains a two-channel Direct Memory Access Controller (DMAC). Each channel performs fast data transfers between any two locations in the memory map initiated by specific peripheral events or software triggers. The main features of the DMAC are as follows: * Two independent channels * Single-byte and burst transfer modes * 16-bit source and destination address registers (for a 64K byte address space) * 16-bit transfer count registers (for up to 64K bytes transferred before underflow) * Source/Destination register automatic increment/decrement and no-change options * Source/Destination/Transfer count register reload on write or after transfer count register underflow options * Transfer requests from USB (9), MBI (4), external interrupts (4), UART1 (2), UART2 (2), SIO (1), TimerX (1), TimerY (1), Timer1 (1), and software triggers * Closely coupled with USB and MBI for efficient data transfers * Interrupt generated for each channel when their respective transfer count register underflows * Fixed channel priority (channel 0 > channel 1) * Two cycles of required per byte transferred Each channel of the DMAC is made up of the following: * 16-bit source and destination registers * A 16-bit transfer count register * Two mode registers * Status flags contained in a status register shared by the two channels * Control and timing logic
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The 16-bit source and destination registers allow accesses to any two locations in the 64K byte memory area. The 16-bit transfer count register decrements by one for each transfer performed and causes an interrupt and flag to be set when it underflows. The mode registers control the configuration and operation of the DMAC channel associated with the registers. A block diagram of the DMAC is shown in Figure 2-93. The SFR addresses for the two mode, source, destination, and transfer count registers of a channel are the same for each channel. Which channel's registers are accessible is determined by the value of the DMAC Channel Index Bit (DCI) (bit 7 of the DMAC Index and Status Register (DMAIS)). When this bit is a "0", channel 0 registers are accessible, and when this bit is a "1", channel 1 registers are accessible. The configuration of DMAIS and the mode registers are shown in Figure 2-94, Figure 2-95, Figure 2-96, and Figure 2-97.
Interrupts: UART1 Rx & Tx, SIO, ExtInt0, TimerY, CNTR1 Signals: OBE0, IBF0(data), EP1, EP2, EP3 OUT_PKT_RDY or IN_PKT_RDY, EP1 OUT_FIFO_NOT_EMPTY INT Detect, I-flag
Address Bus
Ch 0 Timing Generator
Ch 0 Source Reg
(D0TMS) (D0CEN; D0CRR; D0UMIE; D0SWT; D0HRS3,2,1,0) (DTSC) (D0SRCE, D0SRID, D0RLD)
Ch 0 Destination Reg
Ch 0 Count Reg
(D0DRCE. D0DRID, (DRLDD) D0RLD)
(DRLDD)
Int Gen
(D0DAUE) (D0UF) (D0DWC) (D0DWC) (D0DWC)
DMAC Ch 0 Interrupt
Mode Reg 1 Mode Reg 2
Interrupts: UART2 Rx & Tx, ExtInt1, Timer1, TimerX, CNTR0 Signals: OBE1, IBF1(data), EP1, EP2, EP4 OUT_PKT_RDY or IN_PKT_RDY, EP1 OUT_FIFO_NOT_EMPTY INT Detect, I-flag (D1UF, D1SFI) (D0UF, D0SFI) 15
Ch 0 Source Latch
Ch 0 Destination Latch
0 15 0 15
Ch 0 Count Latch
0
DMAC Channel 0
Data Bus
DMAC Channel 1
Temp Reg
Index & Status Reg
Data Bus
Figure 2-93. DMAC Block Diagram
2.11.1 Operation
Each channel of the DMAC transfers byte data from a source address to a destination address when a selected event occurs. If single-byte transfer mode is enabled, one byte of data is transferred per request. If burst transfer mode is enabled, several bytes can be transferred per request, one byte at a time. A temporary register internal to the DMAC stores the data read from the source address until it is written to the destination address on the next cycle. The transfer of one byte takes two cycles of and causes the CPU and possibly the other DMAC channel to stall during this time. At least one cycle of with the CPU operating must take place between transfers by the same DMAC channel caused by different events or between transfers by the two DMAC channels. The DMAC does not operate during WIT, STP, or Hold states.
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7600 Series M37640E8-XXXF Preliminary Specification
Source, Destination, and Transfer Count Register Operation
The user can choose whether the source and destination register for each channel will increment by one, decrement by one, or remain unchanged after each transfer by setting bits 0 through 3 (DxSRID, DxSRCE, DxDRID, and DxDRCE) of DMAC Channel x Mode Register 1 (DMAxM1) to the appropriate values. The values in the source and destination registers are updated with their reload latch values when the transfer count register underflows. The transfer count register is also reloaded when it underflows, and both a flag (DxUF) and the DMAC interrupt associated with the channel are set. Reload of the source and destination registers due to underflow of the transfer count register can be disabled by setting to "1" the DMAC Register Reload Disable Bit (DRLDD). This bit affects reload for both channel 0 and channel 1. Because the transfer count register is 16-bits wide, up to 65,536 transfers can take place before an underflow and the resulting actions described above occur. If the Channel x Disable After Count Register Underflow Enable Bit (DxDAUE) is set to a "1", then the Channel x Enable Bit (DxCEN) is cleared to a "0" when the transfer count register underflows, disabling channel x of the DMAC. The source, destination, and transfer count registers of a DMAC channel can be updated with their reload latch value at any time by setting to a "1" the DMAC Channel x Register Reload Bit (DxRLD). DMAC Source, Destination, and Transfer Count Register Read and Write Method Read and write operations on the high and low-order bytes of the source, destination, and transfer count registers must be performed in a specific order. Write Method When writing to the source, destination, or transfer count register, the low-order byte is written first. Next, the high-order byte is written. When this is done, the data is placed in the reload latch of the high-order byte of the register and the previously written low-order byte data is placed in the reload latch of the low-order byte. At this point, if the DMAC Channel x Write Control Bit (DxDWC) is "0", the values in the reload latches are also loaded in the low and high-order bytes of the register. If DxDWC is "1", the data in the reload latches are loaded in the register after the transfer count register of the DMAC channel underflows or the DxRLD bit of the DMAC channel is set to a "1". Read Method When reading from the source, destination, or transfer count register, the high-order byte is read first. The low-order byte of the register is then read. The value read from the low-order byte of the register is its value when the high-order byte was read. 2.11.1.2 DMAC Transfer Request Sources
The hardware source for initiating a DMAC transfer for each channel is selectable by setting the DMAC Channel x Hardware Transfer Request Source Bits (DxHRS0, 1, 2, 3) to appropriate values. The choices for channel 0 are the UART1 receive or transmit interrupts, the TimerY interrupt, external interrupt 0, one of three USB endpoint OUT_PKT_RDY signals, one of three USB endpoint IN_PKT_RDY signals, the USB endpoint 1 OUT_FIFO_NOT_EMPTY signal, the OBE0 and IBF0 (data) signals from the MBI, the SIO combined receive/transmit interrupt, and the CNTR1 interrupt. The choices for channel 1 are the UART2 receive and transmit interrupts, the TimerX interrupt, external interrupt 1, one of three USB endpoint OUT_PKT_RDY signals, one of three USB endpoint IN_PKT_RDY signals, the USB endpoint 1 OUT_FIFO_NOT_EMPTY signal, the OBE1 and IBF1 (data) signals from the MBI, the Timer1 interrupt, and the CNTR0 interrupt.
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In addition, each channel has a software trigger that can initiate a DMAC transfer. The software trigger is set by writing a "1" to the DMAC Software Transfer Trigger (DxSWT). The hardware transfer request source for each channel can be disabled by writing a "0" to DxHRS0, 1, 2, and 3. When these bits are all "0", which is the reset state, only the software trigger can be used to initiate a transfer. The initiating source for each channel is latched by the DMAC asynchronously and sampled on the rising edge of . Writing a "1" to the DMAC Channel x Transfer Initiation Source Capture Register Reset bit (DxCRR) causes the initiating source sample latch of the associated DMAC channel to be reset. The sample latch is reset automatically one cycle of after a transfer request is detected. New transfer requests for a channel that occur during a DMAC transfer by that same channel are latched as long as they occur after the sample latch is reset. However, if multiple transfer requests occur during a transfer, only one transfer request will be registered. If an interrupt is chosen as the initiating source for DMAC transfers, its interrupt control bit located in one of the three interrupt control registers of the ICU should be cleared to "0" if the user does not wish to have the interrupt serviced by the CPU. 2.11.1.3 Transfer Features for USB and MBI
In order to make the transfer of data between the USB endpoint FIFOs and the input and output buffers of the MBI more efficient, special features have been included in the transfer request logic of each DMAC channel. These features are enabled for a channel when one of the USB endpoint signals is selected as the hardware transfer request source and the DMAC Channel x USB and MBI Enable Bit (DxUMIE) is set to a "1". These features are only intended to be used with single-byte transfer mode. USB OUT FIFO to MBI Output Buffer Transfers The special features provided by both DMAC channels for transfer of data from a USB OUT FIFO to one of the MBI output buffers help facilitate either packet-by-packet transfers or byte-by-byte transfers. Packet-by-Packet Transfers When a USB endpoint OUT_PKT_RDY signal is selected as the hardware transfer request source for a DMAC channel and the DxUMIE bit of the same channel is set to a "1", a transfer request is generated for that DMAC channel when the OUT_PKT_RDY signal for the chosen USB endpoint is high and output buffer x (where x is "0" for DMAC channel 0 and "1" for DMAC channel 1) of the MBI is empty. The OUT_PKT_RDY signal remains high until all bytes of the packet have been read from the OUT FIFO corresponding to that endpoint. Thus, the first transfer request is generated when the OUT_PKT_RDY signal goes high and subsequent transfer requests are generated each time output buffer x becomes empty. Once the final byte of the received packet has been read, the OUT_PKT_RDY signal automatically goes low (if this option is enabled in the USB block). This in turn causes the source, destination, and transfer count registers of the involved DMAC channel to be reloaded (unless the DRLDD bit is set to a "1") and the DMAC interrupt for the involved channel to be set. In addition, if the DxDAUE bit associated with the channel is "1", the channel's DxCEN bit is automatically cleared to "0", disabling the channel. This feature allows a channel of the DMAC in single-byte transfer mode to automatically transfer a received packet of an endpoint from the endpoint's OUT FIFO to the master CPU (via the MBI) without any intervention by the on-chip CPU. Also, because the source, destination, and transfer count registers are automatically reloaded once the current packet has been completely transferred, on-chip CPU intervention is not needed to set up the DMAC channel for transfer of subsequently received packets, even in the case of reception of a short packet.
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In order for this mode to function correctly, the time from the DMAC writing data to MBI output buffer x (which causes pin OBFx to go high) until the end of a master read of MBI output buffer x) must be greater than 104.167*(3 - (12E6/))ns. For example, if = 12MHz, the delay must be greater than 208.334ns, and if = 6MHz, the delay must be greater than 104.167ns. When is less than or equal to 4MHz, no delay is required. Byte-by-Byte Transfers When the USB endpoint 1 OUT_FIFO_NOT_EMPTY signal is chosen as the hardware transfer request source for a DMAC channel and the DxUMIE bit of the same channel is set to a "1", a transfer request is generated for the DMAC channel if the endpoint 1 OUT FIFO is not empty and output buffer x of the MBI is empty. Thus, a transfer request is generated as soon as new data is received in the endpoint 1 OUT FIFO and the master CPU has read the data previously placed in MBI output buffer x. As is the case when the packet-by-packet method is used, the OUT_PKT_RDY signal goes high once a complete packet has been received. It remains high until all bytes of the packet have been read from the OUT FIFO. When the final byte has been read from the OUT FIFO, the OUT_PKT_RDY signal goes low (if this option is enabled in the USB block), which causes the source, destination, and transfer count registers of the involved DMAC channel to be reloaded (unless the DRLDD bit is set to a "1") and the DMAC interrupt corresponding to the involved channel to be set. Also, if the DxDAUE bit associated with the channel is "1", the channel's DxCEN bit is automatically cleared to "0", disabling the channel. If the last byte of the packet has been read from the OUT FIFO before the end_of_packet signal is received by the USB block, the OUT_PKT_RDY signal will still go high and then low a short period of time later (if this option is enabled in the USB block). This feature allows a channel of the DMAC in single-byte transfer mode to automatically transfer data received for endpoint 1 from the endpoint 1 OUT FIFO to the master CPU (via the MBI) prior to reception of the complete packet. MBI Input Buffer to USB IN FIFO Transfers When a USB endpoint IN_PKT_RDY signal is selected as the hardware transfer request source for a DMAC channel and the DxUMIE bit of the same channel is set to a "1", a transfer request is generated when the IN FIFO associated with the endpoint is not full (with respect to the programmed packet size) and input buffer x of the MBI contains data. The transfer request is not generated if input buffer x contains a command. The IN FIFO associated with an endpoint is not full when IN_PKT_RDY is low. The IN_PKT_RDY signal remains low until a full packet has been written to the IN FIFO. Thus, the first transfer request is generated when the IN_PKT_RDY goes low and subsequent transfer requests are generated when data is written to input buffer x by an external device. Once the full packet has been written to the IN FIFO, the IN_PKT_RDY signal is automatically set to a "1" (assuming this option is enabled in the USB block). In this case, the source, destination, and transfer count registers are not automatically reloaded. Instead, the packet size for the endpoint should be written to the transfer count register at initialization time so that it underflows and reloads the registers once the last byte of the data is transferred from input buffer x to the endpoint's IN FIFO. The feature described above allows a channel of the DMAC, in single-byte transfer mode, to automatically transfer data received from the master CPU (via the MBI) to the endpoint's IN FIFO without any intervention by the on-chip CPU. Additionally, since the IN_PKT_RDY signal associated with the endpoint is automatically set (assuming this option is enabled in the USB block), multiple packets can be transferred by a channel of the DMAC without on-chip CPU intervention. Note however that short packets are not handled automatically and instead require intervention by the onchip CPU.
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7600 Series M37640E8-XXXF Preliminary Specification 2.11.1.4 DMAC Transfer Mode
Mitsubishi Microcomputers
Each channel of the DMAC can be operated in single-byte transfer mode or burst transfer mode. The choice is made by the setting of the Channel x DMAC Transfer Mode Selection Bit (DxTMS). When single-byte transfer mode is selected, one byte of data is transferred per transfer request. When burst transfer mode is selected, the value in the transfer count register determines how many single byte transfers occur per transfer request. For example, if the value in the transfer count register is 001416, 21 transfers will occur before control of the address bus and data bus is given back to the CPU. 2.11.1.5 DMAC Transfer Timing
A DMAC transfer can occur at any point during the execution of an instruction by the CPU. However, at least one cycle of with the CPU operating takes place between transfers by the same DMAC channel caused by different events or between transfers by the two DMAC channels. Also, burst transfers and possibly single-byte transfers are prevented from occurring during interrupt service routines. The transfer initiating sources for the two channels are latched by the DMAC asynchronously and polled on the rising edge of . If a transfer request is seen for both channels, the channel 0 request will be serviced first followed by the channel 1 request. If channel 1 is performing a burst transfer when channel 0 receives a transfer request, the channel 1 transfer is suspended at the end of the next source read/destination write operation. The channel 0 transfer is then serviced. Once the channel 0 transfer completes, the channel 1 transfer automatically continues where it left off. In order to prevent channel 0 from completely shutting out channel 1 transfers, one cycle of a suspended channel 1 transfer is allowed to occur after a channel 0 burst transfer even if another channel 0 transfer request is pending. If the I flag value is "0" and an interrupt with its interrupt control bit set to a "1" occurs during a burst transfer by either channel, the transfer is suspended, allowing the interrupt service routine to be entered. The DMAC Channel x Suspend (due to interrupt service request) Flag (DxSFI) corresponding to the channel whose transfer was suspended is automatically set to a "1" at this time. When the I flag value (which was automatically set to a "1" when the interrupt service routine was entered) becomes a "0" again, the DxSF flag is automatically cleared and the transfer continues where it left off. If a DMAC burst transfer request occurs during the servicing of an interrupt, the transfer does not take place until after the interrupt has been serviced, which is understood to have happened when the I flag becomes a "0". If the DMAC Transfer Suspend Control Bit (DTSC) is set to a "1", both single-byte and burst mode transfers are suspended by interrupts. A suspended DMAC transfer can be re-started in the interrupt service routine by writing a "1" to the DxCEN bit of the suspended channel. Sample timing diagrams are shown in Figure 2-98, Figure 2-99, and Figure 2-100. for a single-byte transfer initiated by a hardware source, a single-byte transfer initiated by the software trigger, and a burst transfer initiated by a hardware source, respectively.
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7600 Series M37640E8-XXXF Preliminary Specification
Address: 003F16 Access: R/W 0016
MSB 7
DCI
Reserved D0UF
DRLDD
DTSC
D1SFI
D1UF
D0SFI
D0UF
LSB 0
D0SFI
D1UF
D1SFI
DTSC
DRLDD
Bit 6 DCI
Reset: DMAC Channel 0 Count Register Underflow Flag (bit 0) 0: Channel 0 transfer count register underflow has not occurred 1: Channel 0 transfer count register underflow has occurred DMAC Channel 0 Suspend (due to interrupt service request) Flag (bit 1) 0: Channel 0 transfer has not been suspended 1: Channel 0 transfer has been suspended DMAC Channel 1 Count Register Underflow Flag (bit 2) 0: Channel 1 transfer count register underflow has not occurred 1: Channel 1 transfer count register underflow has occurred DMAC Channel 1 Suspend (due to interrupt service request) Flag (bit 3) 0: Channel 1 transfer has not been suspended 1: Channel 1 transfer has been suspended DMAC Transfer Suspend Control Bit (bit 4) 0: Only burst transfers are suspended during interrupt servicing 1: Both burst and single-byte transfers are suspended during interrupt servicing DMAC Register Reload Disable Bit (bit 5) 0: Reload of source and destination registers of both channels enabled 1: Reload of source and destination registers of both channels disabled Reserved (Read/Write "0") Channel Index Bit (bit 7) 0: Channel 0 mode, source, destination, and transfer count registers accessible 1: Channel 1 mode, source, destination, and transfer count registers accessible
Figure 2-94. DMAIS Configuration
Address: 004016 Access: R/W Reset: 0016
MSB 7
DxTMS
DxRLD DxSRID
DxDAUE
DxDWC
DxDRCE
DxDRID
DxSRCE
DxSRID
LSB 0
DxSRCE
DxDRID
DxDRCE
DxDWC
DxDAUE
DxRLD
DxTMS
DMAC Channel x Source Register Increment/Decrement Select Bit (bit 0) 0: Increment after transfer 1: Decrement after transfer DMAC Channel x Source Register Increment/Decrement Enable Bit (bit 1) 0: Increment/Decrement disabled (No change after transfer) 1: Increment/Decrement enabled DMAC Channel x Destination Register Increment/Decrement Select Bit (bit 2) 0: Increment after transfer 1: Decrement after transfer DMAC Channel x Destination Register Increment/Decrement Enable Bit (bit 3) 0: Increment/Decrement disabled (No change after transfer) 1: Increment/Decrement enabled DMAC Channel x Data Write Control Bit (bit 4) 0: Write data in reload latches and registers 1: Write data in reload latches only DMAC Channel x Disable After Count Register Underflow Enable Bit (bit 5) 0: Channel x not disabled after count register underflow 1: Channel x disabled after count register underflow DMAC Channel x Register Reload Bit (bit 6) 0: No action (Bit is always read as "0") 1: Setting to "1" causes the source, destination, and transfer count registers of channel x to be reloaded DMAC Channel x Transfer Mode Selection Bit (bit 7) 0: Single-byte transfer mode 1: Burst transfer mode
Figure 2-95. DMAxM1 Configuration
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MSB D0CEN D0CRR D0UMIE D0SWT D0HRS3 D0HRS2 D0HRS1 D0HRS0 7 D0HRS3,2,1,0 DMAC Channel 0 Hardware Transfer Request Source Bits (bits 3, 2, 1, 0) 0000: Disabled 0001: UART1 receive interrupt 0010: UART1 transmit interrupt 0011: TimerY interrupt 0100: External Interrupt 0 0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active) 0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active) 0111: USB EndPoint 3 IN_PKT_RDY signal (falling edge active) 1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active) 1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active) 1011: USB EndPoint 3 OUT_PKT_RDY signal (rising edge active) 1100: MBI OBE0 signal (rising edge active) 1101: MBI IBF0(data) signal (rising edge active) 1110: SIO receive/transmit interrupt 1111: CNTR1 interrupt D0SWT DMAC Channel 0 Software Transfer Trigger (bit 4) 0: No action (Bit is always read as "0") 1: Writing "1" requests a channel 0 transfer D0UMIE DMAC Channel 0 USB and MBI Enable Bit (bit 5) 0: Disabled 1: Enabled D0CRR DMAC Channel 0 Transfer Initiation Source Capture Register Reset (bit 6) 0: No action (Bit is always read as "0") 1: Setting to "1" causes reset of the channel 0 capture register D0CEN DMAC Channel 0 Enable Bit (bit 7) 0: Channel 0 disabled 1: Channel 0 enabled
LSB 0
Address: 004116 Access: R/W Reset: 0016
Figure 2-96. DMA0M2 Configuration
MSB 7
D1CEN
D1CRR
D1UMIE
D1SWT
D1HRS3
D1HRS2
D1HRS1
D1HRS0
LSB 0
Address: 004116 Access: R/W Reset: 0016
D1HRS3,2,1,0 DMAC Channel 1Hardware Transfer Request Source Bits (bits 3, 2, 1, 0) 0000: Disabled 0001: UART2 receive interrupt 0010: UART2 transmit interrupt 0011: TimerX interrupt 0100: External Interrupt 1 0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active) 0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active) 0111: USB EndPoint 4 IN_PKT_RDY signal (falling edge active) 1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active) 1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal(rising edge active) 1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active) 1011: USB EndPoint 4 OUT_PKT_RDY signal (rising edge active) 1100: MBI OBE1 signal (rising edge active) 1101: MBI IBF1(data) signal (rising edge active) 1110: Timer1 interrupt 1111: CNTR0 interrupt D1SWT DMAC Channel 1 Software Transfer Trigger (bit 4) 0: No action (Bit is always read as "0") 1: Writing "1" requests a channel 0 transfer D1UMIE DMAC Channel 1 USB and MBI Enable Bit (bit 5) 0: Disabled 1: Enabled D1CRR DMAC Channel 1 Transfer Initiation Source Capture Register Reset (bit 6) 0: No action (Bit is always read as "0") 1: Setting to "1" causes reset of the channel 1 capture register D1CEN DMAC Channel 1 Enable Bit (bit 7) 0: Channel 1 disabled 1: Channel 1 enabled
Figure 2-97. DMA1M2 Configuration
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7600 Series M37640E8-XXXF Preliminary Specification
out SYNCout RD WR
LDA$zz STA $zz (first cycle)
ADL1, 00 PC + 2
DMAC Transfer
DMA Source Address DMA Dest. Address
STA $zz (last 2 cycles)
PC + 3 ADL2, 00
Next Inst.
PC + 4
Address Data DMAC Transfer
Signal (Port33)
PC
PC + 1
A5
ADL1
Data
85
DMA Data
DMA Data
ADL2
Data
OpCode3
Transfer Request Source (active low) Transfer Request Source Sampling Transfer Request Source Sample Latch Reset Figure 2-98. DMAC Transfer - Hardware Source Initiated
out SYNCout RD WR
LDM #$90, $41 Single cycle Single cycle Single cycle Inst. Inst. Inst.
42,00 PC + 3 OpCode2 PC + 4 OpCode3 PC + 5
DMAC Transfer
DMA Source Address DMA Dest. Address
Next Inst.
PC + 6 OpCode5
Address Data DMAC Transfer
Signal (Port33)
PC
PC + 1
PC + 2
3C
18
41
90
OpCode4
DMA Data
DMA Data
Transfer Request Source (active low) Transfer Request Source Sampling Transfer Request Source Sample Latch Reset Figure 2-99. DMAC Transfer - Software Trigger Initiated
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out SYNCout RD WR
LDA $zz STA $zz (first cycle)
ADL1, 00 PC + 2 DMA Source Address1 85
DMAC Transfer
DMA Dest. Address1 DMA Source Address2
STA $zz (second cycle)
DMA Dest. Address2 PC + 3 ADL2
Address Data DMAC Transfer
Signal (Port33)
PC
PC + 1
A5
ADL1
Data
DMA Data1
DMA Data1
DMA Data2
DMA Data2
Transfer Request Source (active low) Transfer Request Source Sampling Transfer Request Source Sample Latch Reset Figure 2-100. DMAC Transfer - Burst Transfer Mode
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7600 Series M37640E8-XXXF Preliminary Specification
2.12 Special Count Source Generator
Address 002D16 002E16 002F16 Description Special Count Source Generator1 Special Count Source Generator2 Special Count Source mode register Acronym and Value at Reset SCSG1=FF SCSG2=FF SCSM=00
This device has a built-in special count source generator. It consists of two 8-bit timers: SCSG1, and SCSG2 (see Figure 2-101.) The contents of the timer latch, corresponding to each timer, determine the divide ratio. The timers can be written to at any time. The output of the special count source generator can be a clock source for Timer X, SIO and the two UARTs.
SCSGM1 SCSGM3 SCSGM1 SCSG1 Reload Latch (8) SCSG1 (8) SCSGM0
SCSGM1 SCSGM3 SCSG2 Reload Latch (8) SCSG2 (8) SCSGM3 SCSGCLK (To UARTs, Timer X and SIO) Figure 2-101. SCSG Block Diagram SCSGM2
2.12.1 SCSG Operation
The SCSG1 and SCSG2 are both down count timers. When the count of a timer reaches 0016, an underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are loaded into the timer. For the count operation for SCSG1 with the Data Write Mode set to write to the latch only see (Figure 2-102.). A memory map and the initial values after reset of the timers and timer reload latches are detailed above. The divide ratio of each timer is given by 1/(n + 1), where n is the value written to the timer. The output of the first timer (SCSG1) is effectively ANDed with the original clock () to provide a count source for the second timer (SCSG2). This results in a count source of n/(n + 1) being fed to SCSG2. The output of the SCSG is a clock, SCSGCLK. The frequency is calculated as follows:
SCSG1 1 SCSGCLK = * --------------------------- * --------------------------- where SCSG1 is the value written to SCSG1 and SCSG2 is the SCSG1 + 1 SCSG2 + 1
value written to SCSG2.
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Count Source 1 0 n n-1 1 0 m m-1
SCSG1 Contents SCSG1 Underflow SCSG1 Latch Contents
n
m
SCSG1 reload latch contents loaded into SCSG1
Figure 2-102. Timer Count Operation for SCSG1
2.12.2 SCSG Description
2.12.2.1 SCSG1
SCSG1 is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer. Write Method When writing to the timer, the data is placed in the SCSG1 reload latch. At this point, if the SCSG1 Data Write Control Bit (SCSGM0) is "0", the value in the SCSG1 reload latch is also loaded in SCSG1. If SCSGM0 is "1", the data in the SCSG1 reload latch is loaded in SCSG1 after SCSG1 underflows. SCSG1 Count Stop Control If the SCSG1 Count Stop Bit (SCSGM1) (bit 1 of the SCSGM Register) is set to a "1", SCSG1 stops counting. This allows to bypass SCSG1 and act as the clock source for SCSG2. If the SCSGCLK Output Control Bit (SCSGM3) is cleared to "0", SCSGCLK is disabled and SCSG1 stops counting (see Figure 2-103.). 2.12.2.2 SCSG2
SCSG2 is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer. Write Method When writing to the timer, the data is placed in the SCSG2 reload latch. At this point, if the SCSG2 Data Write Control Bit (SCSGM2) is low, the value in the SCSG2 reload latch is also loaded in SCSG2. If SCSGM2 is high, the data in the SCSG2 reload latch is loaded in SCSG2 after SCSG2 underflows.
MSB 7 Reserved Reserved SCSGM0 Reserved Reserved SCSGM3 SCSGM2 SCSGM1 SCSGM0 LSB 0 Address: 002F16 Access: R/W Reset: 0016
SCSGM1
SCSGM2
SCSGM3
Bits 4-7
SCSG1 Data Write Control Bit (bit 0) 0: Write data in latch and timer 1: Write data in latch only SCSG1 Count Stop Bit (bit 1) 0: Count start 1: Count stop SCSG2 Data Write Control Bit (bit 2) 0: Write data in latch and timer 1: Write data in latch only SCSGCLK Output Control Bit (bit 3) 0: SCSGCLK output disabled (SCSG1 and SCSG2 off) 1: SCSGCLK output enabled. Reserved (Read/Write "0")
Figure 2-103. SCSGM Register
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7600 Series M37640E8-XXXF Preliminary Specification
If the SCSGCLK Output Control Bit (SCSGM3) is cleared to "0", SCSGCLK is disabled and SCSG2 stops counting. SCSG2 Output (SCSGCLK) The output signal SCSGCLK (output to the UART and Timer blocks) is controlled by SCSGM3. When the SCSGCLK Output Control Bit (SCSGM3) is cleared to "0", SCSGCLK is disabled.
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2.13 Timers
Address 002016 002116 002216 002316 002416 Description Timer XL Timer XH Timer YL Timer YH Timer 1 Acronym and Value at Reset TXL=FF TXH=FF TYL=FF TYH=FF T1=FF Address 002516 002616 002716 002816 002916 Description Timer 2 Timer 3 Timer X mode register Timer Y mode register Acronym and Value at Reset T2=01 T3=FF TXM=00 TYM=00
Timer 123 mode register T123M=00
This device has five built-in timers: Timer X, Timer Y, Timer 1, Timer 2, and Timer 3. The contents of the timer latch, corresponding to each timer, determine the divide ratio. The timers can be read or written at any time. However, the read and write operations on the high and low-order bytes of the 16-bit timers (Timer X and Y) must be performed in a specific order. The timers are all down count timers; when the count of a timer reaches 0016 (000016 for Timer X and Y), an underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to that timer is set to a "1". The divide ratio of a timer is given by 1/(n + 1), where n is the value written to the timer. When the STP instruction is executed or RESET is asserted, 0116 is loaded into Timer 2 and the Timer 2 reload latch, and FF16 is loaded into Timer 1 and the Timer 1 reload latch. Figure 2-107. is a block diagram of the five timers.
2.13.1 Timer X
Timer X is a 16-bit timer that has a 16-bit reload latch, and can be placed in one of four modes by setting bits TXM4 and TXM5 (bits 4 and 5 of the Mode Register, TXM). The bit assignment of the TXM is shown in Figure 2-104.
Bit5 -TXM5 0 0 1 1 Bit4 -TXM4 0 1 0 1 Timer X Mode Timer mode Pulse output mode Event counter mode Pulse width measurement mode
2.13.1.1
Read and Write Method
Read and write operations on the high and low-order bytes of Timer X must be performed in a specific order. Write Method When writing to the timer, the lower order byte is written first. This data is placed in a temporary register that is assigned the same address as Timer XL. Next, the higher order byte is written. When this is done, the data is placed in the Timer XH reload latch and the low-order byte is transferred from its temporary register to the Timer XL reload latch. At this point, if the Timer X Data Write Control Bit (TXM0) (bit 0) is "0", the value in the Timer X reload latch is also loaded in Timer X. If TXM0 is "1", the data in the Timer X reload latch is loaded in Timer X after Timer X underflows.
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Timers
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Address: 002716 Access: R/W Reset: 0016
MSB 7
TXM7
TXM6 TXM0
TXM5
TXM4
TXM3
TXM2
TXM1
TXM0
LSB 0
TXM2,1
TXM3
TXM5,4
TXM6
TXM7
Timer X Data Write Control Bit (bit 0) 0: Write data in latch and timer 1: Write data in latch only Timer X Frequency Division Ratio Bits (bits 2,1) Bit 2 Bit 1 0 0: divided by 8 0 1: divided by 16 1 0: divided by 32 1 1: divided by 64 Timer X Internal Clock Select (bit 3) 0: /n 1: SCSGCLK (from chip special count source generator) Timer X Mode Bits (bits 5,4) Bit 5 Bit 4 0 0: Timer Mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 Polarity Select Bit (bit 6) 0: For event counter mode, clocked by rising edge For pulse output mode, start from high level output For CNTR0 interrupt request, falling edge active For pulse width measurement mode, measure high period 1: For event counter mode, clocked on falling edge For pulse output mode, start from low level output For CNTR0 interrupt request, rising edge active For pulse width measurement mode, measure low period Timer X Stop Bit (bit 7) 0: Count start 1: Count stop
Figure 2-104. TXM Register
Read Method When reading Timer X, the high-order byte is read first. Reading the high-order byte causes the values of Timer XH and Timer XL to be placed in temporary registers assigned the same addresses as Timer XH and Timer XL. The low-order byte of Timer X is then read from its temporary register. This operation assures the correct reading of Timer X while it is counting. 2.13.1.2 Count Stop Control
If the Timer X Count Stop Bit (TXM7) (bit 7 of the TXM) is set to a "1", Timer X stops counting in all four modes. 2.13.1.3 Timer Mode /n (where n is 8, 16, 32, or 64) or SCSGCLK
Count Source:
In this mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a "1", the contents of the timer latch are loaded into the timer, and the count down sequence begins again. 2.13.1.4 Pulse Output Mode /n (where n is 8, 16, 32, or 64) or SCSGCLK
Count Source:
Each time the timer X underflows, the output of the CNTR0 pin is inverted, and the corresponding Timer X interrupt request bit is set to a "1". The repeated inversion of the CNTR0 pin output produces a rectangular waveform with a duty ratio of 50 percent. The initial level of the output is determined by the CNTR0 polarity select bit (bit 6). When this bit is low, the output starts from a high level. When this bit is high, the output starts from a low level.
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7600 Series M37640E8-XXXF Preliminary Specification 2.13.1.5 Event Counter Mode CNTR0
Mitsubishi Microcomputers
Count Source:
Timer countdown is triggered by inputs to the CNTR0 pin. Each time a timer underflows, the corresponding timer interrupt request bit is set to a "1", the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. The edge used to clock Timer X is determined by the CNTR0 polarity select bit (bit 6). 2.13.1.6 Pulse Width Measurement Mode /n (where n is 8, 16, 32, or 64) or SCSGCLK
Count Source:
This mode measures either the high or low-pulse width of the signal on the CNTR0 pin. The pulse width measured is determined by the CNTR0 polarity select bit (bit 6). When this bit is "0", the high pulse is measured. When this bit is "1", the low pulse is measured. The timer counts down while the level on the CNTR0 pin is the polarity selected by the CNTR0 polarity select bit. When the timer underflows, the Timer X interrupt request bit is set to a "1", the contents of the timer reload latch are reloaded into the timer, and the timer continues counting down. Each time the signal polarity switches to the inactive state, a CNTR0 interrupt occurs indicating that the pulse width has been measured. The width of the measured pulse can be found by reading Timer X during the CNTR0 interrupt service routine.
2.13.2 Timer Y
Timer Y is a 16-bit timer that has a 16-bit reload latch, and can be placed in any of four modes by setting TYM4 and TYM5 (bits 4 and 5) (see Figure 2-105.). The desired mode is selected by modifying the values of TYM4 and TYM5.
Bit5 - TYM5 0 0 1 1 Bit4 -TYM4 0 1 0 1 Timer Y Mode Timer mode Pulse period measurement mode Event counter mode HL Pulse width measurement mode
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
TYM7
TYM6 TYM0
TYM5
TYM4
TYM3
TYM2
TYM1
TYM0
TYM1
TYM3,2
TYM5,4
TYM6
TYM7
Access: R/W Timer Y Data Write Control Bit (bit 0) Reset: 0016 0: Write data in latch and timer 1: Write data in latch only Timer Y Output Control Bit (bit 1) 0: TYOUT output disable 1: TYOUT output enable Timer Y Frequency Division Ratio Bits (bit 3,2) Bit 2 Bit 1 0 0: divided by 8 0 1: divided by 16 1 0: divided by 32 1 1: divided by 64 Timer Y Mode Bits (bits 5,4) Bit 2 Bit 1 0 0: Timer mode 0 1: Pulse period measurement mode 1 0: Event counter mode 1 1: HL pulse width measurement mode (continuously measures high period and low period) CNTR1 Polarity Select Bit (bit 6) 0: For event counter mode, clocked by rising edge For pulse period measurement mode, falling edge detection For CNTR1 interrupt request, falling edge active For TYOUT, start on high output 1: For event counter mode, clocked on falling edge For pulse period measurement mode, rising edge detection For CNTR1 interrupt request, rising edge active For TYOUT, start on low output Timer Y Stop Bit (bit 7) 0: Count start 1: Count stop
LSB 0
Address: 002816
Figure 2-105. TYM Register
2.13.2.1
Read and Write Method
Read and write operations on the high and low-order bytes of Timer Y must be performed in a specific order. Write Method When writing to the timer, the lower order byte is written first. This data is placed in a temporary register that is assigned the same address as Timer YL. Next, the high-order byte is written. Then, the data is placed in the Timer YH reload latch and the low-order byte is transferred from its temporary register to the Timer YL reload latch. At this point, if the Timer Y Data Write Control Bit (TYM0) (bit 0) is low, the value in the Timer Y reload latch is also loaded in Timer Y. If TYM0 is "1", the data in the Timer Y reload latch is loaded in Timer Y after Timer Y underflows. Read Method When reading Timer Y, the high-order byte is read first. Reading the high-order byte causes the values of Timer YH and Timer YL to be placed in temporary registers that are assigned the same addresses as Timer YH and Timer YL. The low-order byte of Timer Y is then read from its temporary register. This operation assures the correct reading of Timer Y while it is counting. 2.13.2.2 Count Stop Control
If the Timer Y Count Stop Bit (TYM7) (bit 7) is set to a "1", Timer Y stops counting in all four modes. 2.13.2.3 Timer Mode /n (where n is 8, 16, 32, or 64)
Count Source:
In this mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a "1", the contents of the timer latch are loaded into the timer, and the count down sequence begins again. In Timer mode, the signal TYOUT can also be brought out on the CNTR1 pin. This is controlled by TYM1 (bit1).
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Each time the Timer Y underflows, the output of the CNTR1 pin is inverted, and the corresponding Timer Y interrupt request bit is set to a "1". The repeated inversion of the CNTR1 pin output produces a rectangular waveform with a duty ratio of 50 percent. The initial level of the output is determined by the CNTR1 polarity select bit (bit 6). When this bit is low, the output starts from a high level. When this bit is high, the output starts from a low level. 2.13.2.4 Pulse Period Measurement Mode /n (where n is 8, 16, 32, or 64).
Count Source:
This mode measures the period of the event waveform input to the CNTR1 pin. CNTR1 Polarity Select Bit (TYM6) = "0" When the falling edge of an event waveform is detected on the CNTR1 pin, the contents of Timer Y are stored in the temporary register that is assigned the same address as Timer Y. Simultaneously, the value in the Timer Y reload latch is transferred to Timer Y, and Timer Y continues counting down. The falling edge of an event waveform also causes the CNTR1 interrupt request; therefore, the period of the event waveform from falling edge to falling edge is found by reading Timer Y in the CNTR1 interrupt routine. The data read from Timer Y is the data previously stored in its temporary register. CNTR1 Polarity Select Bit (TYM6) = "1" When the rising edge of an event waveform is detected on the CNTR1 pin, the contents of Timer Y are stored in the temporary register that is assigned the same address as Timer Y. Simultaneously, the value in the Timer Y reload latch is transferred to Timer Y, and Timer Y continues counting down. The rising edge of an event waveform also causes the CNTR1 interrupt request; therefore, the period of the event waveform from rising edge to rising edge is found by reading Timer Y in the CNTR1 interrupt routine. The data read from Timer Y is the data previously stored in its temporary register. Each time the timer underflows, the Timer Y interrupt request bit is set to a "1", the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. 2.13.2.5 Event Counter Mode CNTR1
Count Source:
Timer countdown is triggered by input to the CNTR1 pin. Each time a timer underflows, the corresponding timer interrupt request bit is set to a "1", the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. The edge used to clock Timer Y is determined by the CNTR1 polarity select bit (bit 6). When these bits are "0"s, the timers are clocked on the rising edge. When these bits are "1"s, the timers are clocked on the falling edge 2.13.2.6 HL Pulse-width Measurement Mode /n (where n is 8, 16, 32, or 64).
Count Source:
This mode continuously measures both the logical high pulse width and the logical low pulse width of an event waveform input to the CNTR1 pin. When the falling (or rising) edge of the event waveform is detected on the CNTR1 pin, the contents of Timer Y are stored in the temporary register that is assigned the same address as Timer Y, regardless of the setting of the CNTR1 polarity select bit. Simultaneously, the value in the Timer Y reload latch is transferred to Timer Y, which continues counting down. The falling or rising edge of an event waveform causes the CNTR1 interrupt request; therefore, the width of the event waveform from the falling or rising edge to rising or falling edge is found by reading Timer Y in the CNTR1 interrupt routine. The data read from Timer Y is the data previously stored in its temporary register.
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Timers
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Each time the timer underflows, the Timer Y interrupt request bit is set to a "1", the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again.
2.13.3 Timer 1
MSB 7 T123M7 T123M6 T123M0 T123M5 T123M4 T123M3 T123M2 T123M1 T123M0 LSB 0 Address: 002916 Access: R/W Reset: 0016
T123M1
T123M2
T123M3
T123M4
T123M5
T123M6
T123M7
TOUT Source Selection Bit (bit 0) 0: TOUT = Timer 1 output 1: TOUT = Timer 2 output Timer 1 Stop Bit (bit 1) 0: Timer running 1: Timer stopped Timer 1 Count Source Select Bit (bit 2) 0: divided by 8 1: XCin divided by 2 Timer 2 Count Source Select Bit (bit 3) 0: Timer 1 underflow signal 1: Timer 3 Count Source Select Bit (bit 4) 0: Timer 1 underflow signal 1: divided by 8 TOUT Output Active Edge Selection Bit (bit 5) 0: Start on high output 1: Start on low output TOUT Output Control Bit (bit 6) 0: TOUT output disabled 1: TOUT output enabled Timer 1 and 2 Data Write Control Bit (bit 7) 0: Write data in latch and timer 1: Write data in latch only
Figure 2-106. T123M Register
Timer 1 is an 8-bit timer with an 8-bit reload latch and has a pulse output option. T123M7 of Timer123 mode register (T123M) is the Timer 1 and 2 Data Write Control Bit. If T123M7 is "1", data written to Timer 1 is placed only in the Timer 1 reload latch. The latch value is loaded into Timer 1 after Timer 1 underflows. If T123M7 is "0", the value written to Timer 1 is placed in Timer 1 and the Timer 1 reload latch. At reset, T123M7 is set to a "0". The output signal TOUT is controlled by T123M5 and T123M6. T123M5 controls the polarity of TOUT. Setting the bit T123M5 to "1" causes TOUT to start at a low level, and clearing this bit to "0" causes TOUT to start at a high level. Setting T123M6 to "1" enables TOUT, and clearing T123M6 to "0" disables TOUT. 2.13.3.1 Timer Mode /8 or XCin/2
Count Source:
In Timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a "1", the contents of the timer latch are loaded into the timer, and the count down sequence begins again. 2.13.3.2 Pulse Output Mode /8 or XCin/2
Count Source:
Timer 1 Pulse Output mode is enabled by setting T123M6 to "1" and T123M0 to a "0". Each time the Timer 1 underflows, the output of the TOUT pin is inverted, and the corresponding Timer 1 interrupt request bit is set to a "1". The repeated inversion of the TOUT pin output produces a rectangular waveform with a duty ratio of 50 percent. The initial level of the output is determined by the TOUT polarity select bit (T123M5). When this bit is "0", the output starts from a high level. When this bit is "1", the output starts from a low level.
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.13.4 Timer 2
Timer 2 is an 8-bit timer with an 8-bit reload latch. T123M7 (bit 7 of T123M) is the Timer 1 and 2 Data Write Control Bit. If T123M7 is "1", data written to Timer 2 is placed only in the Timer 2 reload latch (see Figure 2-50). The latch value is loaded into Timer 2 after Timer 2 underflows. If the T123M7 is "0", the value written to Timer 2 is placed in Timer 2 and the Timer 2 reload latch. At reset, T123M2 is set to a "0". The Timer 2 reload latch value is not affected by a change of the count source. However, because changing the count source may cause an inadvertent countdown of the timer, the timer should be rewritten when the count source is changed. 2.13.4.1 Timer Mode If T123M3 is "0", the Timer 2 count source is the Timer 1 underflow output. If T123M3 is "1", the Timer 2 count source is . In Timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a "1", the contents of the timer latch are loaded into the timer, and the count down sequence begins again. 2.13.4.2 Pulse Output Mode If T123M3 is "0", the Timer 2 count source is the Timer 1 underflow output. If T123M3 is "1", the Timer 2 count source is . Timer 2 Pulse Output mode is enabled by setting T123M6 to a "1" and T123M0 to a "1". Each time the Timer 2 underflows, the output of the TOUT pin is inverted, and the corresponding Timer 2 interrupt request bit is set to a "1". The repeated inversion of the TOUT pin output produces a rectangular waveform with a duty ratio of 50 percent. The initial level of the output is determined by the TOUT polarity select bit (T123M5). When this bit is "0", the output starts from a high level. When this bit is "1", the output starts from a low level.
Count Source:
Count Source:
2.13.5 Timer 3
Timer 3 is an 8-bit timer with an 8-bit reload latch. The Timer 3 reload latch value is not affected by a change of the count source. Because changing the count source may cause an inadvertent countdown of the timer, the timer should be rewritten whenever the count source is changed. 2.13.5.1 Timer Mode If T123M4 is "0", the Timer 3 count source is the Timer 1 underflow output. If T123M4 is "1", the count source is /8 In Timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a "1", the contents of the timer latch are loaded into the timer, and the count down sequence begins again. Data written to Timer 3 is always placed in Timer 3 and the Timer 3 reload latch.
Count Source:
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
SCSGCLK
1
TXM3
TXM2,1
Timer X Divider
(1/n) 0
n=8, 16, 32, 64
TYM3,2 Timer Y Divider
(1/n)
TXM5,4
TXM0
00 01
11
TXM7 Timer XL Latch(8) Timer XH Latch(8) Timer XL (8) Timer XH (8)
Timer X Interrupt Request
1/8
10 1
CNTR0
CNTR0 Interrupt Request TXM6 TXM5,4= 01 TXM6
0 Q T 1 Q
0
TXM5, 4 = 01
TYM5,4= 11 Rising Edge Detector Falling Edge Detector TYM5,4= 01 or 11 TYM0 TYM5,4
00 01 11
TYM7
Timer YL Latch(8)Timer YH Latch(8) Timer YH (8) Timer YL (8)
11
Timer Y Interrupt Request TYM5,4
00 01 10
CNTR1
1
10
TYM6
0
CNTR1 Interrupt Request
TYM1= 11 and TYM5,4 = 0 TYM6
0 Q 1 Q S T
TYM= 1 & TYM5, 4 = 00
T123M7 XCin/2 T123M5
0 Q T 1 QS
1 0
T123M2
T123M7 Timer 1 Latch(8) Timer 1 (8) T123M3
1
Timer 2 Latch(8) Timer 2 (8)
Timer 2 Interrupt Request
0
TOUT
T123M0 0 T123M6= 1 T123M6= 1
1 0 Q T 1 QS
T123M1
Timer 1 Interrupt Request
T123M5
0
T123M6 =1
T123M4
1
Timer 3 Latch(8) Timer3 (8)
Timer 3 Interrupt Request
Figure 2-107. Block Diagram of Timers X, Y, 1, 2, and 3
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7600 Series M37640E8-XXXF Preliminary Specification
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2.14 UART
Address 003016 003116 003216 003316 003416 003516 003616 UART1 Description UART1 mode register UART1 baud rate generator UART1 status register UART1 control register UART1 transmit/receiver buffer 1 UART1 transmit/receiver buffer 2 UART1 RTS control register Pin UTXD1 URXD1 CTS1 RTS1 Acronym and Value at Reset U1MOD=00 U1BRG=XX U1STS=03 U1CON=00 U1TRB1=XX U1TRB2=XX U1RTSC=00 Address 003816 003916 003A16 003B16 003C16 003D16 003E16 Pin UTXD2 URXD2 CTS2 RTS2 UART2 Description UART2 mode register UART2 baud rate generator UART2 status register UART2 control register UART2 transmit/receiver buffer 1 UART2 transmit/receiver buffer 2 UART2 RTS control register Description UART2 transmit pin is multiplexed with P80 UART2 receive pin is multiplexed with P81 UART2 CTS2 pin is multiplexed with P82 UART2 RTS2 pin is multiplexed with P83 Acronym and Value at Reset U2MOD=00 U2BRG=XX U2STS=03 U2CON=00 U2TRB1=XX U2TRB2=XX U2RTSC=00
Description UART1 transmit pin is multiplexed with P84 UART1 receive pin is multiplexed with P85 UART1 CTS1 pin is multiplexed with P86 UART1 RTS1 pin is multiplexed with P87
This chip * * * * * * * * * * *
contains two identical UARTs. Each UART has the following main features: Clock selection: or SCSGCLK Prescaler selection: x1/x8/x32/x256 divisions (both and SCSGCLK) Baud rate: 11.4 bits/second - 750 Kbytes/second (at = 12MHz) Error detection: parity/framing/overrun/error sum Parity: odd/even/none Stop bits: 1 or 2 Character length: 7, 8, or 9 bits Transmit/receive buffer: 2 stages (double buffering) Handshaking: Clear-to-Send (CTS) and Request-to-Send (RTS) Interrupt generation conditions: Transmit Buffer Empty or Transmit Complete, Receive Buffer full and Receive Error Sum. Address mode for multi-receiver environment
The following descriptions apply to both UARTs. The UART receives parallel data from the core or DMAC, converts it into serial data, and transmits the results to the send data output terminal UTXDx. The UART receives serial data from an external source through the receive data input URXDx, converts it into parallel data, and makes it available to the core or DMAC. The UART can detect parity, overrun, and framing errors in the input stream and report the appropriate status information. A double buffering configuration is used for the UART's transmit and receive operations. This double buffering is accomplished by the use of a transmit buffer and transmit shift register on the transmit side and the receive buffer and receive shift register on the receive side.
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
The UART generates the Transmit interrupt when either the Transmit Buffer Empty Flag (TBE) or the Transmit Complete Flag (TCM) are set, depending on the state of the Transmit Interrupt Source Selection Bit (TIS, bit 4 of UxCON). The UART generates the Receive Buffer Full interrupt when receiving and the Receive Buffer Full Flag is set to a "1". The Receive Error Sum interrupt is generated instead of a Receive Buffer Full interrupt if the UART detects an error when receiving. Enabling a transmit or receive operation by setting the TEN or the REN (bits 0 and 1 of UxCON) automatically forces the corresponding UART port pins in the appropriate direction. The UART supports an address mode for use in a multi-receiver environment where an address is sent before each message to designate which UART or UARTs are to wake-up and receive the message. Figure 2-108 is a block diagram of the UART. It is valid for both UART1 and UART2.
Data Bus
UART Mode Register UART Status Register UART Control Register
Tx Buffer Empty Tx Enable Tx Complete
UxMOD
UxSTS
UxCON
Transmit Buffer
TBE
TIS = "0"
TCM
Transmit Shift Register
Transmit Interrupt TIS = "1"
Transmit line to UTXDx From CTSx
ST/STP/PA Generator
CTS_SEL Data Bus RTS_SEL CLKSEL SCSGCLK
Clock Set Prescaler /1/8/32/256 Baud Rate Generator RTS Control Register Stop and Start Detect
To RTSx
PS 1,0
LE 1,0; PEN; STB
Data Format Bit Counter
LE 1,0; PEN; STB
Rx Enable Rx Status Errors
Receive Shift Register
Data Format Bit Counter
Receive line from URXDx
Rx Complete
Receive Buffer Full Interrupt
Receive Buffer Register
Receive Error Interrupt Data Bus
Figure 2-108. UART Block Diagram
2.14.1 Baud Rate Selection
UART rate selection is controlled by the UxBRG and is calculated as follows: Baud Rate = f/[16 x (n + 1)] where n denotes the decimal value set in the UxBRG, and where f denotes the clock frequency that depends on the clock selection and the prescale value chosen. Either an internal clock or the output of the chip special count source generator (SCSGCLK) can be selected as the input clock source by means of the UART Clock Selection Bit (CLK, bit 0 of the UART Mode Register (UxMOD)). Bits PS0 and PS1 of the UxMOD are used to select a prescaling factor for the clock. When the internal clock is selected, f is the prescaled value of the internal clock . f = /1, /8, /32, or /256
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The correspondence between prescale values and baud rate for = 12MHz is given as an example in Table 2-4. When SCSGCLK is selected, f is the prescaled value of SCSGCLK. f = SCSGCLK/1, SCSGCLK/8, SCSGCLK/32 or SCSGCLK/256 Example settings for SCSGCLK, which is controlled by Special Count Source Generator registers 1 and 2 (SCSG1,2), the Prescaler and UxBRG for several common baud rates when = 12MHz are given in Table 2-5.
Table 2-4. Prescale Value and Baud Rate Table = 12MHz
/1
n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 . . . . . . . . . . . . 255 Baud Rate 750,000.0 375,000.0 250,000.0 187,500.0 150,000.0 125,000.0 107,142.9 93,750.0 83,333.3 75,000.0 . . . . . . . . . . . . . . . . 2,929.7 0 1 2 3 4 5 6 7 8 . . . . . . . . . . 255 n
/8
Baud Rate n
/32
Baud Rate n
/256
Baud Rate
93,750.0 46,875.0 31,250.0 23,437.5 18,750.0 15,625.0 13,392.9 . . . . . . . . . . . 366.2 0 1 2 3 4 5 6 7 8 . . . . . . . 255 23,437.5 11,718.8 7,812.5 5,859.4 4,687.5 3,906.3 3,348.2 2,929.7 2,604.2 . . . . . . . 91.6 0 1 2 3 4 5 6 . . 255 2,929.7 1,464.8 976.6 732.4 585.9 488.3 418.5 . . 11.44
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Table 2-5. SCSGCLK, Prescaler, and UxBRG settings for common baud rates when = 12MHz Baud Rate SCSG (Hz) (Hex) 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200. 9600 14400 19200 28800 31250 38400 57600 115200 bypassed bypassed 4E AC bypassed bypassed 18 bypassed 18 bypassed 18 18 18 18 18 18 23 18 23 0B SCSG2 SCSGCLK Rate UxBRG Actual Baud Rate Prescaler (Hex) (Hz) (Hex) (Hz) 95 63 43 37 31 18 0B 18 13 18 13 13 0E 13 0E 09 00 00 00 00 80000.00 120000.00 174236.78 213047.07 240000.00 480000.00 960000.00 480000.00 576000.00 480000.00 576000.00 576000.00 768000.00 576000.00 768000.00 1152000.00 11666666.66 11520000.00 12000000.00 11666666.66 12000000.00 11000000.00 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 63 63 62 62 63 63 63 18 13 0E 0E 09 09 04 04 04 25 18 17 12 0C 05 50.00 75.00 110.00 134.50 150.00 300.00 600.00 1200.00 1800.00 2000.00 2400.00 3600.00 4800.00 7200.00 9600.00 14400.00 19188.60 28800.00 31250.00 38377.19 57692.31 114583.33
bypassed bypassed bypassed bypassed
2.14.2 UART Mode Register
UxMOD defines data formats and selects the clock to be used (see Figure 2-109).
MSB 7 LE1 LE0 CLK PEN PMD STB PS1 PS0 CLK LSB 0 Address: 003016, 003816 Access: R/W Reset: 0016
PS1,0
STB
PMD
PEN
LE1,0
UART Clock Selection Bit (bit 0) 0: 1: SCSGCLK Internal Clock Prescaling Selection Bits (bits 2,1) Bit 2 Bit 1 0 0: Division by 1 0 1: Division by 8 1 0: Division by 32 1 1: Division by 256 Stop Bits Selection Bit (bit 3) 0: 1 1: 2 Parity Selection Bit (bit 4) 0: Even 1: Odd Parity Enable Bit (bit 5) 0: Off 1: On Uart Character Length Selection Bits (bits 7,6) Bit 7 Bit 6 0 0: 7 bits/character 0 1: 8 bits/character 1 0: 9 bits/character 1 1: Reserved
Figure 2-109. UxMOD Register
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.14.3 UART Control Register
The UxCON specifies the initialization and enabling of a transmit/receive process (see Figure 2-110). Data can be read from and written to the Control Register.
MSB 7 AME TEN RTS_SEL CTS_SEL TIS RIN TIN REN TEN LSB Address: 003316,003B16 0 Access: R/W 0016
REN
TIN
RIN
TIS
CTS_SEL
RTS_SEL
AME
Transmission Enable Bit (bit 0) Reset: 0: Disable the transmit process 1: Enables the transmit process. If the transmit process is disabled (TEN cleared) during transmission, the transmit will not stop until completed. Receive Enable Bit (bit 1) 0: Disable the receive process 1: Enables the receive process. If the receive process is disabled (REN cleared) during reception, the receive will not stop until completed. Transmission Initialization Bit (bit 2) 0: No action. 1: Resets the UART transmit status register bits as well as stopping the transmission operation. The TEN bit must be set and the transmit buffer reloaded in order to transmit again. The TIN is automatically reset one cycle after TIN is set. Receive Initialization Bit (bit 3) 0: No action. 1: Clears the UART receive status flags and the REN bit. If RIN is set during receive in progress, receive operation is aborted. The RIN bit is automatically reset one cycle after RIN is set. Transmit Interrupt Source Selection Bit (bit 4) 0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set. 1: Transmit interrupt occurs when the Transmit Complete flag is set. Clear-to-Send (CTS) Enable Bit (bit 5) 0: CTS function is disabled, P86 (or P82) is used as GPIO pin. 1: CTS function is enabled, P86 (or P82) is used as CTS input. Request-to-Send (RTS) Enable Bit (bit 6) 0: RTS function is disabled, P87 (or P83) is used as GPIO pin. 1: RTS function is enabled, P87 (or P83) is used as RTS output. UART Address Mode Enable Bit (bit 7) 0: Address Mode disabled. 1: Address Mode enabled.
Figure 2-110. UxCON Register
2.14.4 UART Baud Rate Register
In the UART Baud Rate Register (UxBRG), any value can be specified to obtain the desired baud rate. This register remains in effect whether the UART state is send-enabled, receive-enabled, transmitin-progress, or receive-in-progress. The contents of this register can be modified only when the UART is not in any of these four states.
2.14.5 UART Status Register
The UART Status Register (UxSTS) reflects both the transmit and receive status (see Figure 2-111). The status register is read only. The MSB is always "0" during a read operation. Writing to this register has no effect. Status flags are set and reset under the conditions indicated below. The setting and resetting of the transmit and receive status are not affected by transmit and receive enable flags. The setting and resetting of the receive error flags and receive buffer full flag differs when UART address mode is enabled. These differences are described in section "2.14.9 UART Address Mode". Receive Error Sum Flag The Receive Error Sum Flag (SER) is set when an overrun, framing, or parity error occurs after completion of a receive operation. It is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by setting the Receive Initialization Bit (RIN). If the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read.
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7600 Series M37640E8-XXXF Preliminary Specification
The Receive Overrun Flag (OER) is set if the previous data in the low-order byte of the receive buffer (UxTRB1) is not read before the current receive operation is completed. It is also set if a receive error occurred for the previous data and the status register is not read before the current receive operation is completed. This flag is reset when the status register is read. This flag is also reset when the hardware reset is asserted or the receiver is initialized by RIN. If the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. Receive Framing Error Flag The Receive Framing Error Flag (FER) is set when the stop bit of the received data is "0". If the Stop Bit Selection Bit (STB, bit 3 of UxMOD) is set, the flag is set if either of the two stop bits is a "0". This flag is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by RIN. If the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. Receive Parity Error Flag The Receive Parity Error Flag (PER) is set when the parity of received data and the Parity Selection Bit (PMD, bit 4 of UxMOD) are different. It is enabled only if the Parity Enable Bit (PEN, bit 5 of UxMOD) is set. This flag is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by RIN. If the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. Receive Buffer Full Flag The Receive Buffer Full Flag (RBF) is set when the last stop bit of the data is received. It is not set when a receive error occurs. This flag is reset when the low-order byte of the receive buffer (UxTRB1) is read, the hardware reset is asserted, or the receive process is initialized by RIN. If the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. Transmission Complete Flag In the case where no data is contained in the transmit buffer, the Transmission Complete Flag (TCM) is set when the last bit in the transmit shift register is transmitted. In the case where the transmit buffer does contain data, the TCM flag is set when the last bit in the transmit shift register is transmitted if TBE is a "0" or CTS handshaking is enabled and CTSx is "1". The TCM flag is also set when the hardware reset is asserted or when the transmitter is initialized by setting the Transmit Initialization Bit (TIN, bit 2 of UxCON). It is reset when a transmission operation begins. Transmission Buffer Empty Flag The Transmission Buffer Empty Flag (TBE) is set when the contents of the transmit buffer are loaded into the transmit shift register. The TBE flag is also set when the hardware reset is asserted or when the transmitter is initialized by TIN. It is reset when a write operation is performed to the low-order byte of the transmit buffer (UxTRB1).
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MSB 7
Reserved
SER TCM
OER
FER
PER
RBF
TBE
TCM
LSB Address: 003216, 003A16 0 Access: R only Reset: 0316
TBE
RBF
PER
FER
OER
SER
Bit 7
Transmit-Complete (Transmission Register Empty) Flag (bit 0) 0: Data in the transmission register. 1: No data in the transmission register. TX Buffer Empty Flag (bit 1) 0: Data in the TX Buffer. 1: No data in the TX Buffer. RX Buffer Full Flag (bit 2) 0: No data in the RX Buffer. 1: Data in the RX Buffer. Receive Parity Error Flag (bit 3) 0: No receive parity error. 1: Receive parity error. Receive Framing Error Flag (bit 4) 0: No receive framing error. 1: Receive framing error. Receive Overrun Flag (bit 5) 0: No receive overrun. 1: Receive overrun. Receive Error Sum Flag (bit 6) 0: No receive error. 1: Receive error. Reserved (Read "0")
Figure 2-111. UxSTS Register
2.14.6 Transmit/Receive Format
Transmit Method (See Figure 2-112.) Setup * Define the baud rate by writing a value from 0-255 into the UxBRG. * Set the Transmission Initialization Bit (TIN, bit 2 of UxCON), to "1". This will reset the transmit status to a value of 0316. * Select the interrupt source to be either TBE or TCM by clearing or setting the Transmit Interrupt Source Selection Bit (TIS, bit 4 of UxCON). * Configure the data format and clock selection by writing the appropriate value to UxMOD. * Set the Clear-To-Send Enable Bit (CTS_SEL, bit 5 of UxCON), if CTS handshaking will be used. * Set the Transmit Enable Bit (TEN, bit 0 of UxCON), to "1". Operation * When data is written to the low-order byte of the transmit buffer (UxTRB1), TBE is cleared to "0". If 9-bit character length has been selected, the high-order byte of the transmit buffer (UxTRB2) should be written before the low-order byte (UxTRB1). * If no data is being shifted out of the transmit shift register and CTS handshaking is disabled, the data written to the transmit buffer is transferred to the transmit shift register and the TCM flag in UxSTS is cleared to a "0". In addition, the TBE flag is set to a "1", signalling that the next byte of data can be written to the transmit buffer. If CTS handshaking is enabled, the operation described above does not take place until CTSx is brought low. * Data from the transmit shift register is transmitted one bit at a time beginning with the start bit and ending with the stop bit. Note that the LSB is transmitted first. * If the TEN bit is cleared to a "0" while data is still being transmitted, the transmitter will continue until the last bit is sent. This is also the case when CTS handshaking is enabled and CTSx is brought back high during transmission. 2-96 7/9/98 UART
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* When the last bit is transmitted, the TCM flag is set to a "1" if the transmit buffer is empty, TEN is a "0", or CTS handshaking is enabled and CTSx is "1". If the transmit buffer is not empty, TEN is a "1", and CTS handshaking is disabled or CTS handshaking is enabled and CTSx is low, the TCM flag is not set because transfer of the contents of the transmit buffer to the transmit shift register occurs immediately.
UxBRG Clock UxTRB1 Write TBE
TCM
UTXDx
Start bit
D0
Stop bit
Start bit
Stop bit
Figure 2-112. UART Transmit Operation Waveforms
Receive Method (See Figure 2-113.) Set up * Define the baud rate by writing a value from 0-255 into UxBRG. * Set the Receive Initialization Bit (RIN, bit 3 in the UxCON), to "1". * Configure the data format and the clock selection by writing the appropriate value to UxMOD. * Set the Request-To-Send Enable Bit (RTS_SEL, bit 6 of UxCON), if RTS handshaking will be used. * Set the Receive Enable Bit (REN, bit 1 in the UxCON), to "1". Operation * When a falling edge is detected on the URXDx pin, the value on the pin is sampled at the basic clock rate, which is 16 times faster than the baud rate. If the pin is low for at least two cycles of the basic clock, the start bit is detected. Sampling is again performed three times in the approximate middle of the start bit. If two or more of the samples are low, the start bit is deemed valid. If two or more of the samples are not low, the start bit is invalidated and the UART again begins waiting for a falling edge on the URXDx pin. * Once a valid start bit has been detected, input data received through the URXDx pin is read one bit at a time, LSB first, into the receive shift register. As is the case with the start bit, three samples are taken in the approximate middle of each data bit, the parity bit, and the stop bit(s). If two or more of the samples are low, a "0" is latched, and if two or more of the samples are high, a "1" is latched. * When the number of bits specified by the data format has been received and the last stop bit is UART 7/9/98 2-97
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detected, the contents of the receive shift register are transferred to the receive buffer and the Receive Buffer Full Flag in the UxSTS is set to a "1", if a receive error has not occurred. The RBF interrupt request is also generated at this time if a receive error has not occurred. However, if a receive error did occur, the appropriate error flags are set and the Receive Error Sum (SER) interrupt request is generated at this time. * When the low-order byte of the receive buffer (UxTRB1) is read, the Receive Buffer Full Flag is cleared, and the receive buffer is now ready for the next byte. If 9-bit character length has been selected, the high-order byte of the receive buffer (UxTRB2) should be read before reading the low-order byte (UxTRB1).
URXDx UxBRG Clock
Start bit
D0
Stop bit
Start bit
D0
Edge 2-of-3 detection sampling
2-of-3 sampling
2-of-3 sampling
Edge 2-of-3 detection sampling
2-of-3 sampling
RBF UxTRB1 Read
Figure 2-113. UART Receive Operation Waveforms
2.14.7 Interrupts
The transmit and receive interrupts are generated under the conditions described below. The generation of the receive interrupts differs when UART Address mode is enabled. The differences are described in section "2.14.9 UART Address Mode". Transmit interrupts The UART generates a Transmit interrupt to the CPU core. The source of the Transmit interrupt is selectable by setting TIS. * If TIS = "0", the Transmit interrupt is generated when the transmit buffer register becomes empty (that is, when TBE flag set). * If TIS = "1", the Transmit interrupt is generated after the last bit is sent out of the transmit shift register and no data has been written to the transmit buffer or CTS handshaking is enabled and CTSx is high (that is, when TCM flag set). Receive Interrupts The UART generates the Receive Buffer Full (RBF) and Receive Error Sum (SER) interrupts to the CPU core when receiving. * The RBF interrupt is generated when a receive operation completes and a receive error is not generated. * The SER interrupt is generated when an overrun, framing or parity error occurs.
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2.14.8 Clear-to Send (CTSx) and Request-to-Send (RTSx) Signals
The UART, as a transmitter, can be configured to recognize the Clear-to-Send (CTSx) input as a handshaking signal. As a receiver, the UART can be configured to generate the Request-to-Send (RTSx) handshaking signal. Clear-to-Send (CTSx) Input CTS handshaking is enabled by setting the Clear-to-Send Enable Bit (CTS_SEL, bit 5 of UxCON) to a "1". If CTS handshaking is enabled, when TEN is a "1" and the low-order byte of the transmit buffer (UxTRB1) is loaded, the UART begins the transmission process when the CTSx pin is asserted (low input). After beginning a send operation, the UART does not stop sending until the transmission is completed, even if CTSx is deasserted (high input). If TEN is cleared to "0", the UART will not stop transmitting and the port pins will remain under the control of the UART until the end of the transmission. If CTS handshaking is disabled and TEN is a "1", the UART begins the transmission process as soon as data is available in the low-order byte of the transmit buffer (UxTRB1). Figure 2115 shows a timing example for CTSx. Request-to-Send (RTSx) Output RTS handshaking is enabled by setting the Request-to-Send Enable Bit (RTS_SEL, bit 6 of UxCON) to a "1". When RTS handshaking is enabled, the UART drives the RTSx output low or high based on the following conditions: Assertion conditions (driven low): * The Receive Enable Bit (REN) is set to a "1". * Receive operation has completed with the reception of the last stop bit, REN is still a "1", and the programmable assertion delay has expired. De-assertion conditions (driven high): * A valid start bit is detected and REN is a "1". * REN is cleared to a "0" before a receive operation is in progress. * Receive operation has completed and REN is a "0". * UART Receiver is initialized (RIN is set to a "1"). The delay time from the reception of the last stop bit to the re-assertion of RTSx is programmable. The amount of delay is selected by setting the RTS Assertion Delay Count Bits (RTS3~0, bits 3 to 0 of UxRTSC) (see Figure 2-114). The time can be from no delay to 120 bit-times, with the delay beginning from the middle of the last stop bit. If a start bit is detected before the assertion delay has expired, the delay countdown is stopped and the RTSx pin remains high. A full assertion delay countdown will begin again once the last stop bit of the incoming data has been received. Figure 2-115 shows a timing example for RTSx.
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MSB 7
RTS3 Bits 0-3 RTS3:0
RTS2
RTS1
RTS0
Reserved
Reserved
Reserved
Reserved
LSB Address: 003616, 003E16 0 Access: R/W Reset: 8016
Reserved (Read/Write "0") RTS Assertion Delay Count 3:0 (bits 7,6,5,4) 0000: No delay, RTS asserts immediately after receive operation completes. RTS asserts 8 bit-times after receive operation completes. 0001: RTS asserts 16 bit-times after receive operation completes. 0010: RTS asserts 24 bit-times after receive operation completes. 0011: . . . RTS asserts 64 bit-times after receive operation completes. 1000: . . . RTS asserts 112 bit-times after receive operation completes. 1110: RTS asserts 120 bit-times after receive operation completes. 1111:
Figure 2-114. UxRTSC Register
CTS (input)
TXD (output)
start
DATA
stop RXD (input) DATA
programmable delay start DATA
RTS (output)
In both examples, the Transmit and Receive have already been enabled Figure 2-115. CTSx and RTSx Timing Examples
2.14.9 UART Address Mode
The UART address mode is intended for use in a multi-receiver environment where an address is sent before each message to designate which UART or UARTs are to wake-up and receive the message. An address is identified by the MSB of the incoming data byte being a "1". The bit is "0" for non-address data. UART address mode can be used in either 8-bit or 9-bit character length mode. The character length is chosen by writing the appropriate values to the UART Character Length Selection Bits (LE1,0). UART address mode is enabled by setting the UART Address Mode Enable Bit (AME) to "1". When UART address mode is enabled, the MSB of a newly received byte of data (that is either 8 or 9 bits in length) is examined if a valid stop bit is detected and a parity error has not occurred (if parity is enabled). If the MSB is "1", then the receive buffer full interrupt and flag are set and AME is automatically cleared, disabling UART address mode. If the MSB is "0", then the receive buffer full interrupt is not set. However, the RBF flag is still set for this case. If a valid stop bit is not detected
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or a parity error has occurred, neither the receive buffer full flag nor interrupt is set and the MSB of the data is not examined. Instead, either the framing error or parity error flag is set, the error sum flag is set, and the error sum interrupt is set. While in UART address mode, the generation of overrun errors is disabled after the first byte of data is received. Therefore, when non-address data is received without errors while in the UART address mode, it is not necessary to read the UART receive buffer prior to the reception of the next byte of data. Also, if a framing or parity error occurs while in UART address mode, it is not necessary to read the UxSTS prior to the reception of the next byte of data. However, an overrun error will occur if an address byte is received and the UART receive buffer is not read before a new byte of data is received. This is the case because the UART address mode was automatically disabled when the address byte was received. Also, an overrun error will occur for the first byte received after UART address mode is enabled if the preceding byte received did not generate an error and the UART receive buffer was not read, or the preceding byte did generate an error and UxSTS was not read. When the MSB is "1" and the UART address mode is automatically disabled, the UART reverts back to normal reception mode. In normal reception mode, the value of the MSB of each byte of received data has no effect on the setting of the receive buffer full interrupt or the determination of overrun errors.
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2.15 Serial I/O
Address 002A16 002B16 002C16 Description SIO shift register SIO control register 1 SIO control register 2 Name SRDY SCLK SRXD STXD Pin is multiplexed with P80 is multiplexed with P81 is multiplexed with P82 is multiplexed with P83 Acronym and Value at Reset SIOSHT=XX SIOCON1=00 SIOCON2=00
The Serial I/O has the following main features: * Synchronous transmission or reception * Handshaking via SRDY output signal * 8-bit character length * Interrupt after transmission or reception * Internal Clock (When serial I/O synchronous clock select bit is "1", internal clock source divided by 2, 4, 8, 16, 32, 64, 128, 256 can be selected). If bit 1 of SIO Control Register2 is "0", internal clock source = ; if bit 1 of SIO Control Register2 is "1", internal clock source = SCSGCLK.) * External Clock (When SIO synchronous clock select bit is "1", an external clock input from the SCLK pin is selected). A block diagram of the clock synchronous SIO is shown in Figure 2-116.
2.15.1 SIO Control Register
The Serial I/O Control Register controls the various SIO functions (see Figure 2-117.). All of this register's bits can be read from and written to by software. At reset, this register is cleared to 0016. The SIO Control Register determines whether the device's pins are used as ordinary I/O ports or as SIO function pins. This register also determines the transfer direction and transfer clock for serial data.
2.15.2 SIO Operation
An internal clock or an external clock can be selected as the synchronous clock. When the internal clock is chosen, dividers are built in to provide eight different clock selections. The start of a transfer is initiated by a write signal to the SIO shift register (address 002A16). The SRDY signal then drops active low. On the negative edge of the transfer clock SRDY returns high and the data is transmitted out the STXD pin. Data is latched in from the SRXD pin on the rising edge of the transfer clock. If an internal clock is selected, the STXD pin enters a high-impedance state after an 8-bit transfer is completed. If an external clock is selected, the contents of the serial I/O register continue to be shifted while the send/receive clock is being input. Therefore, the clock needs to be controlled by the external source. Also there is no STXD high-impedance function after data is transferred.
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Regardless of whether an internal or external clock is selected, after an 8-bit transfer, the interrupt request bit is set. Figure 2-119 shows the timing for the serial I/O with the LSB-first option selected. The SIO can be operated in slave mode. In slave mode the SRDY pin becomes an input from a master. If SRDY is held high, the shift clock is inhibited, STXD is tri-stated, and shift count is reset. If SRDY is held low, then the normal shift operation is performed.
SRXD STXD SCLK SRDY SCSGCLK
RDYSel
PSel
PSel SIO Shift Register
1
0
1
0 SRDY
1
0
P81 Latch
P80 Latch
CLKSEL
P83 Latch
0
1
Synchronous Circuit SCSel
External Clock
SIO Counter
SLAVE
0
1
Divider
1/64 1/128 1/32 1/8 1/4 1/256 1/16 1/2
Data Bus SIO Interrupt Request Figure 2-116. Clock Synchronous SIO Block Diagram
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MSB 7
OCHCont
SCSel ISCSel0-2
TDSel
RDYSel
PSel
ISCSel2
ISCSel1
ISCSel0
LSB 0
Address: 002B16 Access: R/W Reset: 0016
PSel
RDYSel
TDSel
SCSel
OCHCont
Internal Synchronization Clock Select Bits (bits 2,1,0) Bit 2 Bit 1 Bit 0 0 0 0: Internal Clock divided by 2. 0 0 1: Internal Clock divided by 4. 0 1 0: Internal Clock divided by 8. 0 1 1: Internal Clock divided by 16. 1 0 0: Internal Clock divided by 32. 1 0 1: Internal Clock divided by 64. 1 1 0: Internal Clock divided by 128. 1 1 1: Internal Clock divided by 256. SIO Port Selection Bit (bit 3) 0: I/O Port 1: TxD output, SCLK function SRDY Output Select Bit (bit 4) 0: I/O Port 1: SRDY signal Transfer Direction Select Bit (bit 5) 0: LSB first 1: MSB first Synchronization Clock Select Bit (bit 6) 0: External Clock 1: Internal Clock TxD Output Channel Control Bit (bit 7) 0: CMOS output 1: N-Channel open drain output
Figure 2-117. SIO Control Register 1
MSB 7
Reserved
Reserved
Reserved
Reserved
Reserved
RXDSel
CLKSEL
SLAVE
LSB 0
Address: 002C16 Access: R/W Reset: 1816
SLAVE
CLKSEL
RXDSel
Bits 3-4 Bits 5-7
Slave Mode Selection Bit (bit 0) 0: Normal mode 1: Slave mode (to enter Slave mode, bit 4 of SIO Control register 1 also needs to be set) SIO Internal Clock Selection Bit (bit 1) 0: 1: SCSGCLK SRXD Input Selection Bit (bit 2) 0: SRXD input disabled 1: SRXD input enabled Reserved (Read/Write "1") Reserved (Read/Write "0")
Figure 2-118. SIO Control Register 2 Synchronous Clock Transfer Clock SIO Register Write Signal Receive Enable Signal SRDY SIO Output SIO Input Interrupt Request Bit Set When the internal clock is selected, the TxD pin goes into highimpedance after the data is transferred. D0 D1 D2 D3 D4 D5 D6 D7
See Note
Note:
Figure 2-119. Normal Mode SIO Function Timing (with LSB-First selected)
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2.16 Low Power Modes
This device has two low-power dissipation modes: * Stop * Wait
2.16.1 Stop Mode
Use of the stop mode allows the mcu to be placed in a state where no internal excitation of the circuitry is taking place, thus resulting in extremely low power dissipation. The mcu enters the stop mode when the STP instruction is executed. The internal state of the mcu after execution of the STP instruction is as follows: * All internal oscillation stops with P2 and P2PER held high and P1 and P1PER held low. * Timer 1 and Timer 2 are loaded with FF16 and 0116 respectively. * The count source for Timer 1 is set to /8 and the count source for Timer 2 is set to Timer 1 underflow.
Xin out P1 P2 P1PER P2PER INTREQ STPSIG CPUOSC SYNCout RD WR Address Data
PC Opcode PC + 1 Invalid S,CPMA2
(PC + 1)H
Timer Countdown (Oscillator stabilization) Timer 2 underflow Note: Return from a STP Instruction is caused by an interrupt, followed by the countdown and underflow of Timer 2 Sleep Period
Start of Interrupt Service Routine
Figure 2-120. STP Cycle Timing Diagram
Oscillation is restarted (that is, all clocks other than P1 and P2 begin to oscillate) when a reset or an external interrupt is received. The interrupt control bit of the interrupt used to release the stop mode must be set to a "1" and the I flag set to a "0" prior to the execution of the STP instruction. To allow the oscillation source time to stabilize, the oscillation source is connected as the clock source for the wake-up timer (Timer 1 and Timer 2 cascaded). When Timer 2 underflows, the system clocks P1 and P2 are restarted and the mcu services the interrupt that caused the return from the stop state. It Low Power Modes 7/9/98 2-105
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then services any other enabled interrupts that occurred, in the order of their respective priorities, and returns to its state prior to the execution of the STP instruction. The timing for the STP instruction is shown in Figure 2-120.
2.16.2 Wait Mode
Use of the wait mode allows the microcomputer to be placed in a state where excitation of the CPU is stopped, but the clocks to the peripherals continue to oscillate. This mode provides lower power dissipation during the idle periods and quick wake-up time. The microcomputer enters the wait mode when the WIT instruction is executed. After the instruction execution, P2 is held high and P1 is held low. Returning from wait mode is accomplished just as it is when returning from stop mode, with the exception that you need not provide time for the oscillator to stabilize, because the oscillation never stopped. Because P1PER and P2PER continue to oscillate in the wait mode, any peripheral interrupt can be used to bring the microcomputer out of the wait mode. The timing for the WIT instruction is shown in Figure 2-121.
Xin out P1 P2 P1PER P2PER INTREQ STPSIG SYNCout RD WR Address Data
PC
PC + 1 Invalid
Sleep Period
S,CPMA2
(PC + 1)H
Opcode
Note: Return from a WIT instruction is caused by an interrupt.
Start of Interrupt Service Routine
Figure 2-121. WIT Cycle Timing Diagram
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2.17 Reset
This device is reset if the RESET pin is held low for a minimum of 2s while the supply voltage is between 4.75 and 5.25Volts. When the RESET pin returns high, the reset sequence commences (see Figure 2-122). To allow the oscillation source the time to stabilize, a delay is generated by the countdown of Timer 1 and Timer 2 cascaded with FF16 loaded in Timer 1 and 0116 loaded in Timer 2. After the reset sequence completes, program execution begins at the address whose high-order byte is the contents of address FFFA16 and whose low-order byte is the contents of address FFFB16.
out P1 P2 Reset SYNCout Address Data ? ? Timer countdown from 01FF16 Figure 2-122. Internal Processing Sequence after RESET ? ? ? ? ? ? ? ? FFFA ADH FFFB
ADL, ADH First Opcode
ADL
Reset
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2.18 Key-On Wake-Up
This device contains a key-on wake-up interrupt function. The key-on wake-up interrupt function is one way of returning from a power-down state caused by the STP or WIT instructions. This interrupt is generated by applying low level to any pin of Port 2. If a key matrix is connected as shown in Figure 2-123, the microcomputer can be returned to a normal state by pressing any one of the keys. Key-on wake-up is enabled in single-chip mode only.
Port PXx L level output from arbitrary port Xx
Key-on wake up Interrupt Request
Pull P2 register bit 7
Port P27 latch
Port P2 direction register bit 7 = 1
P27 output
Pull P2 register bit 6
Port P26 latch
Port P2 direction register bit 6 = 1
P26 output
Pull P2 register bit 5
Port P25 latch
Port P2 direction register bit 5 = 1
P25 output
Pull P2 register bit 4
Port P24 latch
Port P2 direction register bit 4 = 1
P24 output Port P2 input read circuit
Pull P2 register bit 3
Port P23 latch
Port P2 direction register bit 3 = "0"
P23 input
Pull P2 register bit 2
Port P22 latch
Port P2 direction register bit 2 = "0"
P22 input
Pull P2 register bit 1
Port P21 latch
Port P2 direction register bit 1 = "0"
P21 input
Pull P2 register bit 0
Port P20 latch
Port P2 direction register bit 0 = "0"
P20 input
Off Chip On Chip
Figure 2-123. Port 2 with Key-on Wake-up Function
2-108
7/9/98
Key-On Wake-Up
MITSUBISHI SEMICONDUCTOR AMERICA, INC.
PRELIMINARY
Chapter 3
Electrical Characteristics
3.1 Absolute Maximum Ratings. . . .3-3 3.2 Recommended Operating conditions . . . . . . . . . . . . . . . . . 3-4 3.3 Electrical Characteristics . . . . . 3-6 3.4 Timing Requirements and Switching Characteristics . . . . 3-8
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
3-2
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
3 Electrical Characteristics
3.1
Symbol VCC AVCC VI VI VI VI VO PD TOPR TSTG Power supply Analog power supply Input voltage P0, P1, P2, P3, P4, P5, P6, P7, P8 Input voltage RESET, Xin, XCin Input voltage CNVSS Input voltage USB D+, DOutput voltage P0, P1, P2, P3, P4, P5, P6, P7, P8, Xout, XCout Power dissipationNote 1 Operating temperature Storage temperature Ta = 25C Values are with respect to VSS. Output transistors are in off state.
Absolute Maximum Ratings
Table 3-1. Absolute Maximum Ratings Parameter Conditions Limits -0.3 to 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to 13 -0.5 to 3.8V -0.3 to VCC + 0.3 750 -20 to +85 -40 to +125 Unit V V V V V V V mW C C
Note 1. Maximum power dissipation is based on package heat dissipation characteristics, not chip power consumption.
Absolute Maximum Ratings
6/2/98
3-3
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
3.2
Recommended Operating conditions
Table 3-2. Recommended Operating Conditions
(VCC = 4.15 to 5.25V, VSS = 0V, Ta = -20 to 85C, unless otherwise noted)
Symbol VCC AVCC VSS AVSS VIH VIH VIH VIH VIL VIL VIL VIL Supply voltage Analog supply voltage Supply voltage Analog supply voltage H input voltage H input voltage H input voltage H input voltage L input voltage L input voltage L input voltage L input voltage
Parameter
Limits Min.
4.15 4.15
Typ.
5 5 0 0
Max.
5.25 VCC
Unit
V V V V
RESET, Xin, XCin, CNVSS P0, P1, P2, P3, P4, P5, P6, P7, P8 P2
(When PTC6 = "0")
0.8VCC 0.8VCC 0.5VCC 2.0 0 0 0 0
VCC VCC VCC VCC 0.2VCC 0.2VCC
0.16VCC 0.8
V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz MHz KHz/MHz
P57-P54, P6, P72
(When MBI inputs and PTC7 = "1")
RESET, Xin, XCin, CNVSS P0, P1, P2, P3, P4, P5, P6, P7, P8 P2
(When PTC6 = "0")
P57-P54, P6, P72
(When MBI inputs and PTC7 = "1")
IOL (peak) L peak output current Note 1 IOL (avg) L average output current Note 2 IOH (peak) H peak output current Note 1 IOH (avg) H average output current Note 2 OL (peak) IOL (avg) IOH (peak) IOL (avg) L total peak output current Note 3 L total average output current Note 4 H total peak output current Note 3 H total average output current Note 4
P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8
10 5 -10 -5 80 40 -80 -40 5 5 24 32.768 50/5.0
f(CNTR0) TimerX - input frequency Note 5 f(CNTR1) TimerY - input frequency Note 5 f(Xin) f(XCin) Clock frequency Note 5 Clock frequency Note 5,6
Note 1. The peak output current is the peak current flowing through any pin of the listed ports. Note 2. The average output current is an average current value measured over 100ms. Note 3. The total peak output current is the peak current flowing through all pins of the listed ports.
3-4
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Recommended Operating conditions
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Note 4. The total average output current is an average current value measured over 100ms. Note 5. The oscillation frequency has a 50% duty cycle. Note 6. The maximum oscillation frequency of 50KHz is for a crystal oscillator connected between XCin and XCout. An external clock signal having a maximum frequency of 5MHz can be input to XCin.
Recommended Operating conditions
6/2/98
3-5
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
3.3
Electrical Characteristics
Table 3-3. Electrical Characteristics
(VCC = 4.15 to 5.25V, VSS = 0V, Ta = -20 to 85C, unless otherwise noted)
Symbol VOH VOL H output current L output current
Parameters P0, P1, P2, P3, P4, P5, P6, P7, P8 P0, P1, P2, P3, P4, P5, P6, P7, P8 CNTR0, CNTR1, INT0, INT1, Keyon wakeup (P2), RDY, HOLD Ioh = -10mA Iol = 10mA
Test Conditions
Limits Min Typ. Max
VCC 2.0 2.0 0.5 0.5 0.5 5
Unit
V V V V V A A A A A A A A A A V
VT + ~VT-
Hysteresis
URXD1, URXD2 (SCLK), CTS2 (SRXD), SRDY, CTS1 RESET P0, P1, P2, P3, P4, P5, P6, P7, P8 RESET, CNVSS Xin XCin P0, P1, P3, P4, P5, P6, P7, P8 P2 Vi = VSS Vi = VSS (Pullups off) VCC = 5V, Vi = VSS (Pullups on)
-30
IIH
H input current
Vi = VCC
5 9 20 5 -5 -5 -70 -140 -5
IIL
L input current RESET CNVSS Xin XCin RAM retention voltage Vi = VSS
-9
-20 -20 -5
VRAM
Clocks stopped f(Xin) = 24MHz, = 6MHz, USB operating, frequency synthesizer onNote 1 Normal Mode f(Xin) = 24MHz, = 12MHz, USB operating, frequency synthesizer onNote 1 f(Xin) = 24MHz, = 12MHz, USB suspended, frequency synthesizer on, USB clock disabledNote 2
2.0
55 70
70 90
mA mA
35
45
mA
ICC
Supply current (Output transistors are isolated) Wait Mode
f(Xin) = 24MHz, = 12MHz, USB suspended, frequency synthesizer on, USB clock disabledNote 3 f(XCin) = 32KHz, = 16KHz, USB disabled, frequency synthesizer off, transceiver voltage converter offNote 4 Transceiver voltage converter on with USBC3 = "1" (low current mode)
7.5
10
mA
6
10
A
200 0.1
250 1 10
A A A
Stop Mode
Ta = 25C, transceiver voltage converter off Ta = 85C, transceiver voltage converter off
3-6
6/2/98
Electrical Characteristics
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Note 1. Icc test conditions: Single chip mode (run state) Square wave clock input on Xin (Xout drive disabled) I/O pins isolated Frequency synthesizer running USB operating with transceiver voltage converter enabled CPU and DMAC running Timers and SCSG running Both UARTs transmitting MBI and SIO disabled Note 2. Icc test conditions same as Note 1 except for the following: USB in suspend state with USB clock disabled Note 3. Icc test conditions: Single chip mode (wait state) Square wave clock input on Xin (Xout drive disabled) I/O pins isolated Frequency synthesizer running USB in suspend state with USB clock disabled Transceiver voltage converter enabled Timers and SCSG running CPU and DMAC not running Both UARTs, SIO, and MBI disabled Note 4. Icc test conditions: Single chip mode (wait state) Xin/Xout oscillation disabled Square wave clock input on XCin (XCout drive disabled) I/O pins isolated Frequency synthesizer disabled USB and USB clock disabled Transceiver voltage converter disabled Timers and SCSG running CPU and DMAC not running Both UARTs, SIO, and MBI disabled
Electrical Characteristics
6/2/98
3-7
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
3.4
Timing Requirements and Switching Characteristics
Table 3-4. Timing Requirements and Switching Characteristics
(VCC = 4.15 to 5.25V, VSS = 0V, Ta = -20 to 85C, unless otherwise noted)
Symbol
Parameter
INPUTS
Min.
2 41.66 0.4*tc(Xin) 0.4*tc(Xin) 200 0.4*tc(XCin) 0.4*tc(XCin) INTERRUPTS 140 55 55 200 80 80 TIMERS
Limits Typ.
Max.
Unit
s ns ns ns ns ns ns
tw(RESET) tc(Xin)
twh(Xin) twl(Xin) tc(XCin) twh(XCin) twl(XCin) tc(INT) twh(INT) twl(INT) tc(CNTRI) twh(CNTRI) twl(CNTRI)
RESET input "Low" pulse width Clock input cycle time Clock input "High" pulse width Clock input "Low" pulse width Clock input cycle time Clock input "High" pulse width Clock input "Low" pulse width
INT0, INT1 input cycle time INT0, INT1 input "High" pulse width INT0, INT1 input "Low" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "High" pulse width CNTR0, CNTR1 input "Low" pulse width TIMER TOUT delay time Note 1 TIMER CNTR0 delay time (pulse output mode) Note 1 TIMER CNTR0 input cycle time (event counter mode)
ns ns ns ns ns ns
td(-TOUT) td(-CNTR0) tc(CNTRE0) twh(CNTRE0) twl(CNTRE0) td(-CNTR1) tc(CNTRE1) twh(CNTRE1) twl(CNTRE1)
15 15 200
ns ns ns ns ns
TIMER CNTR0 input "High" pulse width (event counter mode) 0.4*tc(CNTRE0) TIMER CNTR0 input "Low" pulse width (event counter mode) TIMER CNTR1 delay time (pulse output mode) Note 1 TIMER CNTR1 input cycle time (event counter mode) 200
0.4*tc(CNTRE0)
15
ns ns ns ns
TIMER CNTR1 input "High" pulse width (event counter mode) 0.4*tc(CNTRE1) TIMER CNTR1 input "Low" pulse width (event counter mode) SIO
0.4*tc(CNTRE1)
tc(SCLKE) twh(SCLKE) twl(SCLKE) tsu(SRXD-SCLKE) th(SCLKE-SRXD) td(SCLKE-STXD) tv(SCLKE-SRDY) tc(SCLKI) twh(SCLKI) twl(SCLKI) tsu(SRXD-SCLKI) th(SCLKI-SRXD) td(SCLKI-STXD)
SIO external clock input cycle time SIO external clock input "High" pulse width SIO external clock input "Low" pulse width SIO receive setup time (external clock) SIO receive hold time (external clock) SIO transmit delay time (external clock) SIO SRDY valid time (external clock) SIO internal clock output cycle time SIO internal clock output "High" pulse width SIO internal clock output "Low" pulse width SIO receive setup time (internal clock) SIO receive hold time (internal clock) SIO transmit delay time (internal clock)
400 190 180 15 10 25 26 166.66
0.5*tc(SCLKI)-5 0.5*tc(SCLKI)-5
ns ns ns ns ns ns ns ns ns ns ns ns 5 ns
20 5
3-8
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Timing Requirements and Switching Characteristics
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
Table 3-4. Timing Requirements and Switching Characteristics
(VCC = 4.15 to 5.25V, VSS = 0V, Ta = -20 to 85C, unless otherwise noted)
Symbol
Parameter
MBI (Separate R and W Type Mode)
Min.
0 0 0 0 10 10 0 0 50 50 25 0
Limits Typ.
Max.
Unit
tsu(S-R) tsu(S-W) th(R-S) th(W-S) tsu(A-R) tsu(A-W) th(R-A) th(W-A) tw(R) tw(W) tsu(D-W) th(W-D) ta(R-D) tv(R-D) tv(R-OBF) td(W-IBF)
S0, S1 setup time for read S0, S1 setup time for write S0, S1 hold time for read S0, S1 hold time for write A0 setup time for read A0 setup time for write A0 hold time for read A0 hold time for write Read pulse width Write pulse width Data input setup time before write Data input hold time after write Data output enable time after read Data output disable time after read OBF output transmission time after read IBF output transmission time after write MBI (R/W Type Mode)
ns ns ns ns ns ns ns ns ns ns ns ns 40 ns ns 40 40 ns ns
10
tsu(S-E) th(E-S) tsu(A-E) th(E-A) tsu(RW-E) th(E-RW) tw(E) tw(E-E) tsu(D-E) th(E-D) ta(E-D) tv(E-D) tv(E-OBF) td(E-IBF)
S0, S1 setup time S0, S1 hold time A0 setup time A0 hold time R/W setup time R/W hold time Enable pulse width Enable pulse interval Data input setup time before write Data input hold time after write Data output enable time after read Data output disable time after read OBF output transmission time after E inactive IBF output transmission time after E inactive
0 0 10 0 10 10 50 50 25 0 40 10 40 40
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1. Timer clock is or a derivative of .
Timing Requirements and Switching Characteristics 6/2/98
3-9
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Inputs
RESET
0.2Vcc
tw(RESET)
0.8Vcc
tc(Xin) twh(Xin) twl(Xin)
Xin
0.8Vcc 0.2Vcc
tc(XCin) twh(XCin) twl(XCin)
XCin
0.8Vcc 0.2Vcc
Interrupts
tc(INT), tc(CNTRI) twh(INT),twh(CNTRI) twl(INT),twl(CNTRI)
INT0, INT1, CNTR0, CNTR1
0.8Vcc 0.2Vcc
Timers
0.5Vcc
td(-TOUT)
TOUT
0.5Vcc
td(-CNTR0,1)
CNTR0, CNTR1
0.5Vcc
tc(CNTRE0,1) twh(CNTRE0,1) twl(CNTRE0,1)
CNTR0, CNTR1
0.8Vcc 0.2Vcc
Figure 3-1. Reset, Clock, Interrupts and Timers Timing Diagram
3-10
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Timing Requirements and Switching Characteristics
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
SIO
tc(SCLKE,I) twl(SCLKE,I) twh(SCLKE,I)
0.8Vcc
SCLK
0.2Vcc
tsu(SRXD-SCLKE,I)
0.8Vcc
th(SCLKE,I-SRXD)
SRXD
0.2Vcc
td(SCLKE,I-STXD)
STXD
0.5Vcc
tv(SCLKE-SRDY)
0.8Vcc
SRDY
Figure 3-2. SIO Timing Diagram
Timing Requirements and Switching Characteristics 6/2/98
3-11
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Read
A0
tsu(A-R)
0.8Vcc (2.0V) 0.2Vcc (0.8V)
th(R-A)
tsu(S-R) S0, S1
0.2Vcc (0.8V)
th(R-S)
tw(R) R
0.8Vcc (2.0V) 0.2Vcc (0.8V)
DQ0-DQ7 ta(R-D) OBF tsu(A-W)
0.8Vcc (2.0V) 0.2Vcc (0.8V)
0.8Vcc 0.2Vcc
0.8Vcc 0.2Vcc
tv(R-D)
tv(R-OBF)
0.2Vcc
th(W-A)
Write
A0
tsu(S-W) S0, S1
0.2Vcc (0.8V)
th(W-S)
tw(W) W
0.8Vcc (2.0V) 0.2Vcc (0.8V)
tsu(D-W) DQ0-DQ7
0.8Vcc (2.0V) 0.2Vcc (0.8V)
th(W-D)
td(W-IBF) IBF
Note: TTL input levels in parenthesis (TTL levels selected when PTC7 = "1")
0.2Vcc
Figure 3-3. MBI Timing Diagram (Separate R and W Type Mode)
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Timing Requirements and Switching Characteristics
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
tw(E-E) E
0.2Vcc (0.8V) 0.8Vcc (2.0V) 0.2Vcc (0.8V)
tw(E)
tsu(A-E) A0 R/W
0.8Vcc (2.0V) 0.2Vcc (0.8V)
th(E-A)
tsu(S-E) S0, S1
0.2Vcc (0.8V)
th(E-S)
Read
DQ0-DQ7 ta(E-D)
0.8Vcc 0.2Vcc
tv(E-D) tsu(E-D)
0.8Vcc (2.0V) 0.2Vcc (0.8V)
Write
DQ0-DQ7
th(E-D)
tv(E-OBF) td(E-IBF) OBF, IBF
Note: TTL input levels in parenthesis (TTL levels selected when PTC7 = "1")
0.2Vcc
Figure 3-4. MBI Timing Diagram (R/W Type Mode)
Timing Requirements and Switching Characteristics 6/2/98
3-13
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Table 3-5. Memory Expansion Mode and Microprocessor Mode Timing
(VCC = 4.15 to 5.25V, VSS = 0V, Ta = -20 to 85C, unless otherwise noted)
Symbol
tc() twh() twl() td(-AH) tv(-AH) td(-AL) tv(-AL) td(-WR) tv(-WR) td(-RD) tv(-RD) td(-SYNC) tv(-SYNC) td(-DMA) tv(-DMA) tsu(RDY-) th(-RDY) tsu(HOLD-) th(-HOLD) td(-HLDA) tv(-HLDA) tsu(DB-) th(-DB) td(-DB) tv(-DB) twl(WR) twl(RD) td(AH-WR) td(AL-WR) tv(WR-AH) tv(WR-AL) td(AH-RD) td(AL-RD) tv(RD-AH) tv(RD-AL) tsu(RDY-WR) th(WR-RDY) tsu(RDY-RD) th(RD-RDY) tsu(DB-RD) th(RD-DB) td(WR-DB) tv(WR-DB)
clock cycle time
Parameter
Limits Min.
83.33 0.5*tc()-5 0.5*tc()-5 31 5 33 5 6 3 6 3 6 4 25 5 21 0 21 0 25 25 7 0 22 13 0.5*tc()-5 0.5*tc()-5 0.5*tc()-28 0.5*tc()-30 0 0 0.5*tc()-28 0.5*tc()-30 0 0 27 0 27 0 13 0 20 10
Typ.
Max.
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
clock "H" pulse width clock "L" pulse width
Address bus AB15-AB8 delay time with respect to Address bus AB15-AB8 valid time with respect to Address bus AB7-AB0 delay time with respect to Address bus AB7-AB0 valid time with respect to WR delay time WR valid time RD delay time RD valid time SYNCOUT delay time SYNCOUT valid time DMAOUT delay time DMAOUT valid time RDY setup time with respect to RDY hold time with respect to HOLD setup time HOLD hold time HLDA delay time HLDA valid time Data bus setup time with respect to Data bus hold time with respect to Data bus delay time with respect to Data bus valid time with respect to Note 1 WR pulse width RD pulse width WR delay time after stable address AB15-AB8 WR delay time after stable address AB7-AB0 Address bus AB15-AB8 valid time with respect to WR Address bus AB7-AB0 valid time with respect to WR RD delay time after stable address AB15-AB8 RD delay time after stable address AB7-AB0 Address bus AB15-AB8 valid time with respect to RD Address bus AB7-AB0 valid time with respect to RD RDY setup time with respect to WR RDY hold time with respect to WR RDY setup time with respect to RD RDY hold time with respect to RD Data bus setup time with respect to RD Data bus hold time with respect to RD Data bus delay time with respect to WR Data bus valid time with respect to WR Note 1
Note 1. . Measurement conditions: Iohl = 5ma, CL = 50pF
3-14
6/2/98
Timing Requirements and Switching Characteristics
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
tc( )
twh() twl()
0.5Vcc
0.5Vcc
td( - AH)
tv( - AH)
AB15-AB8
0.5Vcc
td( - AL)
tv( - AL)
AB7-AB0
0.5Vcc
td( - WR) td( - RD)
tv( - WR) tv( - RD)
RD, WR
0.5Vcc
td( - SYNC)
tv( - SYNC)
SYNCOUT
td( - DMA)
0.5Vcc
tv( - DMA)
DMAOUT
0.5Vcc
(n cycles of )
tsu(RDY - ) th( - RDY)
0.8Vcc 0.2Vcc
RDY
tsu(HOLD - ) th( - HOLD)
HOLD (Enter state)
0.8Vcc 0.2Vcc
td( - HLDA)
HLDA
tsu(HOLD - ) th( - HOLD)
0.5Vcc
HOLD (Exit state)
0.8Vcc 0.2Vcc
tv( - HLDA)
HLDA
tsu(DB - )
0.8Vcc
0.5Vcc
th( - DB)
DB0-DB7 (CPU Read Phase) DB0-DB7 (CPU Write Phase)
0.2Vcc
td( - DB) tv( - DB)
0.5Vcc
Figure 3-5. Microprocessor and Memory Expansion Mode Timing Diagram 1
Timing Requirements and Switching Characteristics 6/2/98
3-15
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
twl(RD), twl(WR)
RD, WR
td(AH - WR) td(AH - RD)
0.5Vcc
tv(WR - AH) tv(RD - AH)
AB15-AB8
0.5Vcc
td(AL - WR) td(AL - RD)
tv(WR - AL) tv(RD - AL)
AB7-AB0
0.5Vcc
tsu(RDY - WR) tsu(RDY - RD)
th(WR - RDY) th(RD - RDY)
RDY
0.8Vcc 0.2Vcc
tsu(DB - RD)
0.8Vcc
th(RD - DB)
DB0-DB7 (CPU Read Phase) DB0-DB7 (CPU Write Phase)
0.2Vcc
td(WR - DB) tv(WR - DB)
0.5Vcc
Figure 3-6. Microprocessor and Memory Expansion Mode Timing Diagram 2
1k Measurement output pin Measurement output pin
100pF
100pF
CMOS Output
N-channel Open-drain Output
Figure 3-7. Output Switching Characteristics Measurement Circuits
3-16
6/2/98
Timing Requirements and Switching Characteristics
MITSUBISHI SEMICONDUCTOR AMERICA, INC.
PRELIMINARY
Chapter 4
Application Notes
4.1 DMAC . . . . . . . . . . . . . . . . 4-3 4.2 UART . . . . . . . . . . . . . . . . . 4-4 4.3 Timer . . . . . . . . . . . . . . . . . 4-5 4.4 Frequency Synthesizer Interface . . . . . . . . . . . . . . 4-6 4.5 USB Transceiver . . . . . . . . 4-7 4.6 Using the Frequency Synthesizer and DC-DC Converter. . . . . . . . . . . . . . 4-8 4.7 Ports . . . . . . . . . . . . . . . . 4-12 4.8 Programming Notes . . . . 4-13
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
4-2
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
4 Application Notes
4.1
4.1.1
DMAC
Application
The following is an example of how to set up the DMAC for interfacing with a peripheral block. In this case data is being transferred by DMAC channel 0 from UART1 receive buffer to user RAM. * Write 0816 to DMA0M1 so that after each transfer the destination register will be decremented by one and the source register will remain unchanged. * Write 0016 to the low-order byte of the destination register (DMA0DL) and 0316 to the high-order byte of the destination register (DMA0DH) so that the data received by the UART is placed in page three of the user RAM starting from address 030016. * Write 3416 to the low-order byte of the source register (DMA0SL) and 0016 to the high-order byte of the source register (DMA0SH) so that the DMAC reads from address 003416, which is the loworder byte of the UART receive buffer. * Write to the transfer count register (DMA0CL/H) with a 16-bit value that corresponds to the number of transfers to occur before flag CRUF and the DMAC channel 0 interrupt are set. * Set the DMAC transfer initiating source to the UART receive interrupt by writing 0116 to DMA0M2. * Place the UART in the desired configuration for data reception by writing to the UART control (U1CON), UART mode (U1MOD), and UART baud rate (U1BRG) registers. * Disable the UART receive interrupt from being serviced by the CPU by setting to a "0" bit 6 of interrupt control register A (ICONA). * Enable the DMAC channel 0 interrupt by setting bit 4 of ICONA to "1". * Enable DMAC channel 0 and reset the initiating source sample latch by writing C116 to DMA0M2. The DMA controller will transfer one byte of data from the UART receive buffer to third page user RAM each time that the UART1 receive interrupt is set. Because the destination register is incremented by one after each transfer, third page user RAM is contiguously filled with received data. The transfer count register decrements by one after each transfer. When it underflows, flag D0UF and the DMAC channel 0 interrupt are set. In the DMAC channel 0 service routine, the user can either write new values to the source, destination, and transfer count registers, or leave these registers untouched. If they are left untouched, then they contain the previously written values that were reloaded when the transfer count register underflowed. This would result in the previously transferred UART data in third page user RAM being overwritten with newly received UART data.
DMAC
8/10/98
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
4.2
4.2.1
UART
Application
* 7 bit operation: When 7 bit data format is used, bit 7 of the transmit buffer register 1 is ignored. The transmit buffer register 2 does not affect the 7 or 8 bit format. * 9 bit operation: The upper transmit/receive buffer register (UxTRB2) is a single bit register (bit 0). Writing to the upper bits in these registers has no affect. When reading the register the upper 7 bits are "0". * The RTS Control Register (UxRTSC) is reset to 8016 when the Receive Initialization Bit (RIN) is set to "1". When programming the RTS delay, ensure the RIN bit is set prior to programming the delay. Note: The value in UBRG is not affected by a reset.
4-4
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UART
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
4.3
4.3.1
Timer
Usage
* If Port 43 is read when Timer X Pulse Output mode is being used, the value returned is the pulse output signal fed from the timer to the port. * If Port 44 is read when Timer Y Pulse Output mode is being used, the value returned is the pulse output signal fed from the timer to the port. * If Port 51 is read when Timer1/Timer2 Pulse Output mode is being used, the value returned is the pulse output signal fed from the timer to the port.
Table 4-1. Initial Values of Timer Pulse Outputs Timer Selection Bit Initial Output Value 0: Logic H 1: Logic L 0: Logic H 1: Logic L 0: Logic H 1: Logic L
Timer Y CNTR1 Polarity Select Bit (TXM6) Timer X CNTR0 Polarity Select Bit (TXM6) Timer 1/ Tout Output Active Edge Selection Bit Timer 2 (T123M5)
Timer
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
4.4
Frequency Synthesizer Interface
All passive components should be in close proximity to pin 18 (LPF). The recommended values are as follows:
Table 4-2. Recommended Values R 000 C2=680 pf C1=0.1 f 1/8 watt 5V 5V 10% 10% 10%
See Figure 4-1 for a schematic of the LPF.
Pin 18 (LPF) R C2
C1 Pin 19 Avss
Figure 4-1. LPF Filter Schematic
Analog Vss and Analog Vdd, pins 19 and 17 should have isolated connectors to the digital Vss and Vdd ground planes. Figure 4-2 illustrates the power supply isolation.
Ferrite Beads
Digital Vdd (on card) C Digital Vss
Decoupling Capacitors
Analog Vdd (Pin 17) C Analog Vss (Pin 19)
Figure 4-2. Power Supply Isolation
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Frequency Synthesizer Interface
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
4.5
USB Transceiver
When using the on-chip voltage converter to supply the necessary 3.3V to the driver circuit, a capacitor must be connected between Ext. Cap (pin 72) and VSS (pin 73). The Capacitor spec is as follows: voltage: 5V, tolerance: 10%, type: mica, glass, polystyrene or low-loss ceramic. The recommended value of the capacitor on Ext. Cap is 2.2F in parallel with a 0.1F. The start-up time for this value of the capacitor is 3.2ms. The start-up time is approximately (1ms/F) + 1ms. After enabling the on-chip voltage converter, a certain amount of time must pass before a WIT or STP instruction is executed. The amount of time is given by (C+1)ms, when C is the value in F of the external capacitance connected to the Ext. Cap pin. For example, if the external capacitance is 2.2F, at least 3.2ms must elapse from the time that the on-chip voltage converter is enabled until a WIT or STP instruction is executed. In order to meet the impedance matching requirements of the USB Specification, a 33 resistor must be added to USB D+ (pin 70) and to USB D- (pin 71). In addition, a 33pF capacitor should be connected between USB D+ and USB D- after the 33 resistors. The placement of external components is illustrated in Figure 4-3.
M37640E8
Voltage Converter Ext Cap
2.2 F 0.1 F
USB_Vp_out USB_Txen_n USB_Vm_out USB_Suspend USB_Rxd
XCV_Vp_out XCV_Txen_n XCV_Vm_out XCV_Suspend XCV_Rxd
D+ D-
33 33 pF
33
USB Block
+ _
USB_Vp_in
XCV_Vp_in
USB_Vm_in
XCV_Vm_in
Transceiver
Figure 4-3. Configuration of External USB Components
USB Transceiver
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Mitsubishi Microcomputers
4.6
Using the Frequency Synthesizer and DC-DC Converter
This section presents the recommended method of setting up and using the frequency synthesizer that generates the 48MHz clock needed by the USB FCU and the DC-DC converter that provides power to the D+/D- drivers.
4.6.1
Reset of USB Related Registers
Hardware Reset
SFR Registers: 000016 to 001216, 001316 (USBC), 001416 to 001E16, 001F16 (CCR), 002016 to 004F16, 006C16 (FSC), 006D16 to 006F16
USB Reset
SFR Registers: 005016 to 005E16 (USB FCU registers)
Figure 4-4. SFR Reset Venn Diagram
The special function registers (SFRs) that govern the operation of the frequency synthesizer, DC-DC converter and USB FCU are affected by one or more reset events. The addresses of the special function registers (SFRs) that are affected by Hardware Reset, USB Reset, or both are shown in Figure 4-4. All resettable SFRs, including SFRs and other registers internal to the USB FCU, are affected by a Hardware Reset, which occurs when the RESET pin is brought low or an undefined opcode is fetched. See Table 2.1 for a complete listing of SFRs and their reset values. Only registers internal to the USB FCU are reset when a USB Reset sent by the Host/Hub is detected. These USB registers are reset to their default values except for bit 5 of USBIS2 (USB Reset Interrupt Status Flag), which is set to a "1". USB FCU registers are registers from address 005016 to 005E16 and all other registers within the USB FCU, many of which the MCU does not have direct access to (e.g. FIFO address pointers). The USB FIFO registers are not reset. Other SFRs such as USBC, FSC, and CCR are not affected by a USB Reset.
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
4.6.2
Set up of Frequency Synthesizer and DC-DC Converter
M37640E8
Xin Frequency Synthesizer
enable lock
USBC5 DC-DC Converter
(enable) enable current mode
FSE
LS
USBC4
USBC3
(enable) 2.2 F
Ext Cap
1.5k 0.1 F
D+ USBCLK (48MHz) USB FCU USB Transceiver Denable enable
33 33 pF
33
USBC7 USBC7
Figure 4-5. PLL, DC-DC Converter and USB Functional Block Diagram
A functional block diagram of the USB system on the M37640E8 which shows how the control signals affect operation is given in Figure 4-5. 4.6.2.1 Set up after Hardware Reset
A Hardware Reset occurs when either the RESET pin is brought low for more than 2s or an invalid opcode is fetched by the CPU. The frequency synthesizer (PLL) and DC-DC converter should be set up as follows in the Hardware Reset routine (see Figure 4-6): * Power up the M37640E8 and other components on the peripheral device for less than 100mA operation. The current limit only applies for bus powered devices. * Configure the PLL for 48MHz f(VCO) operation. * Enable the PLL by setting FSE (bit 0 of the Frequency Synthesizer Control Register (FSC)) to a "1", then wait for 2ms. * Check the lock status bit (LS, bit 7 of FSC). * If the bit is a "1", go on. * If the bit is a "0", wait 0.1ms longer and then re-check the bit. * Enable the DC-DC converter in high current mode by setting USBC4 (bit 4 of the USB Control Register (USBC)) to a "1" and keeping USBC3 (bit 3 of USBC) a "0". High current mode should always be used during normal USB operation. Low current mode should only be used during a USB suspend. * Wait (C + 1)ms (where C equals the external capacitance connected to the Ext Cap pin in F) for the voltage on Ext Cap to reach a steady state voltage of approximately 3.3V. (Since the D+ pullup is connected to the Ext Cap pin, the upstream hub will detect that the peripheral device has been plugged in once the voltage on D+ reaches approximately 2.0V.)
Using the Frequency Synthesizer and DC-DC Converter8/10/98
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Mitsubishi Microcomputers
Example: A 2.3F capacitor connected to Ext Cap requires 3.3ms for the voltage on Ext Cap to be stable. * Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1". (If the USB clock and FCU are enabled before the voltage on Ext Cap is stable, a phantom USB Reset may be detected, or the actual USB Reset may not be detected.) * Wait at least 4 cycles of , then enable the USB FCU by setting USBC7 (bit 7 of USBC) to a "1". * Enable other blocks as necessary. RESET FSE Wait 2ms LS Enable DC-DC converter USBC4 Wait (C+1)ms USBC5 Enable USB Clock Wait at least 4 cycles of Enable PLL
USBC7 Enable USB FCU
Figure 4-6. PLL and DC-DC Converter Set Up Timing after Hardware Reset
4.6.2.2
Set up after USB Reset Signaling Detected
A USB Reset is detected by the USB FCU when an SE0 is present on D+/D- for at least 2.5s. Detection of a USB Reset results in bit 5 of USB Interrupt Status Register 2 (USBIS2) being set to a "1" and the registers within the USB FCU being reset to their default values. Register USBC and the PLL registers are not affected by a USB Reset. A USB Function Interrupt request is also generated when the USB Reset is detected. No modifications to the frequency synthesizer or DC-DC converter configuration should be made in the USB Function Interrupt routine. However, all USB FCU registers (addresses 005016 to 005F16) must be reconfigured to their pre-enumeration state. 4.6.2.3 Set up after USB Suspend Detected
A USB Suspend occurs if the USB FCU does not detect any bus activity on D+/D- for at least 3ms. Detection of a suspend results in bit 7 of USBIS2 being set to a "1". If bit 7 of the USB Interrupt Enable Register 2 (USBIE2) is a "1", a USB Function Interrupt request is also generated. The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in the USB Function Interrupt routine (if the device is bus powered): * Disable the USB clock by setting USBC5 (bit 5 of USBC) to a "0". * Disable the PLL by setting FSE (bit 0 of FSC) to a "0".
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
* Change the DC-DC converter from high current mode to low current mode by setting USBC3 (bit 3 of the USBC) to a "1". * Perform other tasks to reduce total current to below 500uA. * Execute the STP instruction. Make sure to enable the USB Suspend/Resume Signaling Interrupt Enable Bit (bit 7 of USBIE2 = "1"), the USB Function Interrupt (bit 0 of IREQA = "1") and clear the I flag prior to executing the STP instruction so the MCU can wake up once resume signaling is detected. Note that no action may be necessary if the device is self powered. 4.6.2.4 Set up after USB Resume Signaling Detected
A resume occurs when the USB FCU is in the suspend state and detects non-idle signaling on D+/D-. Detection of a resume results in bit 6 of USBIS2 being set to a "1". If bit 7 of USBIE2 is a "1", a USB Function Interrupt request is also generated. If the MCU was in the stop state prior to the detection of the resume, the USB Function Interrupt request will cause the MCU to wake up from the stop state. See section 2.16.1 "Stop Mode" for details on waking up from the stop state. The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in the USB Function Interrupt routine (if the device is bus powered): * Change the DC-DC converter from low current mode to high current mode by setting USBC3 (bit 3 of the USBC) to a "0". * Re-enable the PLL for 48MHz f(VCO) by setting FSE (bit 0 of the FSC) to a "1", then wait for 2ms. * Check the lock status bit (LS, bit 7 of FSC). * If the bit is a "1", go on. * If the bit is a "0", wait 0.1ms longer and then re-check the bit. * Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1". * Enable other blocks as necessary. Note that the configuration changes described above may not need to be made if the MCU was not placed in a suspend state as described in section 4.6.2.3 "Set up after USB Suspend Detected".
Using the Frequency Synthesizer and DC-DC Converter8/10/98
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
4.7
Ports
After reset, Port 2 input voltage characteristics are set to 0.5Vcc for VIH and 0.16Vcc for VIL. To change the input voltage characteristics to CMOS levels, set bit 6 of the port control register (PTC) to a "1".
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Ports
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
4.8
Programming Notes
Always execute an SEI instruction immediately before executing a PLP instruction.
Programming Notes
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Mitsubishi Microcomputers
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Programming Notes
MITSUBISHI SEMICONDUCTOR AMERICA, INC.
PRELIMINARY
Chapter 5
SFR Register List
5 Register List . . . . . . . . . . . . . . . . . 5-3
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
5-2
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
5 Register List
MSB 7 CPMA7 CPMA6 CPMA0,1 CPMA5 CPMA4 CPMA3 CPMA2 CPMA1 CPMA0 LSB 0 Address: 000016 Access: R/W Reset: 0C16 Processor Mode Bits (bits 1,0) Bit 1 Bit 0 0 0: Single-Chip Mode 0 1: Memory Expansion Mode 1 0: Microprocessor Mode 1 1: Not used Stack Page Selection Bit (bit 2) 0: In page 0 area 1: In page 1 area Xcout Drive Capacity Selection Bit (bit 3) 0: Low 1: High Clock XCin-XCout Stop Bit (bit 4) 0: Stop 1: Oscillator Clock Xin-Xout Stop Bit (bit 5) 0: Oscillator 1: Stop Internal Clock Selection Bit (bit 6) 0: External Clock 1: fsyn External Clock Selection Bit (bit 7) 0: Xin-Xout 1: XCin-XCout
CPMA2
CPMA3
CPMA4
CPMA5
CPMA6
CPMA7
Figure 5-1. CPU Mode Register A
Address: 000116 Access: R/W Reset: 8316
MSB 7
CPMB7
Reserved
CPMB5
CPMB4
CPMB3
CPMB2
CPMB1
CPMB0
LSB 0
CPMB0,1
CPMB2,3
CPMB4
CPMB5
CPMB6 CPMB7
Slow Memory Wait Bits (bits 1,0) Bit 1 Bit 0 0 0: No wait 0 1: One time wait 1 0: Two time wait 1 1: Three time wait Slow Memory Mode Bit (bits 3,2) Bit 3 Bit 2 0 0: Software wait 0 1: Not used 1 0: Fixed wait by RDY pin L 1 1: Extended RDY wait Expanded Data Memory Access Bit (bit 4) 0: EDMA output disabled (64 Kbyte data access area) 1: EDMA output enabled (greater than 64 Kbytes data access area) HOLD Function Enable Bit (bit 5) 0: HOLD Function Disabled 1: HOLD Function Enabled Reserved (Read/Write "0") Xout Drive Capacity Selection Bit (bit 7) 0: Low 1: High (default state after reset and after STOP mode)
Figure 5-2. CPU Mode Register B
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Address: 000216 Access: R/W Reset: 0016
MSB 7
IRA7
IRA6 IRA0 IRA1 IRA2 IRA3 IRA4 IRA5 IRA6 IRA7
IRA5
IRA4
IRA3
IRA2
IRA1
IRA0
LSB 0
USB Function Interrupt Request (bit 0) USB SOF Interrupt Request (bit 1) External Interrupt 0 Request (bit 2) External Interrupt 1 Request (bit 3) DMAC channel 0 Interrupt Request (bit 4) DMAC channel 1 Interrupt Request (bit 5) UART1 Receive Buffer Full Interrupt Request (bit 6) UART1 Transmit Interrupt Request (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 5-3. IREQA Configuration
MSB 7
IRB7
IRB6 IRB0 IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7
IRB5
IRB4
IRB3
IRB2
IRB1
IRB0
LSB 0
Address: 000316 Access: R/W Reset: 0016
UART1 Error Sum Interrupt Request (bit 0) UART2 Receive Buffer Full Interrupt Request (bit 1) UART2 Transmit Interrupt Request (bit 2) UART2 Error Sum Interrupt Request (bit 3) Timer X Interrupt Request (bit 4) Timer Y Interrupt Request (bit 5) Timer 1 Interrupt Request (bit 6) Timer 2 Interrupt Request (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 5-4. IREQB Configuration
MSB Reserved 7
IRC6 IRC0 IRC1 IRC2 IRC3 IRC4 IRC5 IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
LSB 0
Address: 000416 Access: R/W Reset: 0016
Timer 3 Interrupt Request (bit 0) External CNTR0 Interrupt Request (bit 1) External CNTR1 Interrupt Request (bit 2) SIO Interrupt Request (bit 3) Input Buffer Full Interrupt Request (bit 4) Output Buffer Empty Interrupt Request (bit 5) Key-on Wake-up Interrupt Request (bit 6) 0: No interrupt request issued 1: Interrupt request issued
Bit 7
Reserved (Read/Write "0")
Figure 5-5. IREQC Configuration
MSB 7
ICA7
ICA6 ICA0 ICA1 ICA2 ICA3 ICA4 ICA5 ICA6 ICA7
ICA5
ICA4
ICA3
ICA2
ICA1
ICA0
LSB 0
Address: 000516 Access: R/W Reset: 0016
USB Function Interrupt Enable (bit 0) USB SOF Interrupt Enable (bit 1) External Interrupt 0 Enable (bit 2) External Interrupt 1 Enable (bit 3) DMAC channel 0 Interrupt Enable (bit 4) DMAC channel 1 Interrupt Enable (bit 5) UART1 Receive Buffer Full Interrupt Enable (bit 6) UART1 Transmit Interrupt Enable (bit 7) 0: Interrupt Disable 1: Interrupt Enable
Figure 5-6. ICONA Configuration
5-4
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
ICB7
ICB6 ICC0 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7
ICB5
ICB4
ICB3
ICB2
ICB1
ICB0
LSB 0
Address: 000616 Access: R/W Reset: 0016
UART1 Error Sum Interrupt Enable (bit 0) UART2 Receive Buffer Full Interrupt Enable (bit 1) UART2 Transmit Interrupt Enable (bit 2) UART2 Error Sum Interrupt Enable (bit 3) Timer X Interrupt Enable (bit 4) Timer Y Interrupt Enable (bit 5) Timer 1 Interrupt Enable (bit 6) Timer 2 Interrupt Enable (bit 7) 0: Interrupt Disable 1: Interrupt Enable
Figure 5-7. ICONB Configuration
Address: 000716 Access: R/W Reset: 0016
MSB 7
Reserved
ICC6 ICC0 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6
ICC5
ICC4
ICC3
ICC2
ICC1
ICC0
LSB 0
Timer 3 Interrupt Enable (bit 0) External CNTR0 Interrupt Enable (bit 1) External CNTR1 Interrupt Enable (bit 2) SIO Interrupt Enable (bit 3) Input Buffer Full Interrupt Enable (bit 4) Output Buffer Empty Interrupt Enable (bit 5) Key-on Wake-up Interrupt Enable (bit 6) 0: Interrupt disabled 1: Interrupt enabled
Bit 7
Reserved (Read/Write "0")
Figure 5-8. ICONC Configuration
MSB 7
PTC7
PTC6 PTC0
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
LSB 0
Address: 001016 Access: R/W Reset: 0016
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
Slew Rate Control Bit Ports 0-3 (bit 0) 0: Disabled 1: Enabled Slew Rate Control Bit Port 4 (bit 1) 0: Disabled 1: Enabled Slew Rate Control Bit Port 5 (bit 2) 0: Disabled 1: Enabled Slew Rate Control Bit Port 6 (bit 3) 0: Disabled 1: Enabled Slew Rate Control Bit Port 7 (bit 4) 0: Disabled 1: Enabled Slew Rate Control Bit Port 8 (bit 5) 0: Disabled 1: Enabled Port 2 Input Level Select Bit (bit 6) 0: Reduced VIHL level input 1: CMOS level input Master Bus Input Level Select Bit (bit 7) 0: CMOS level input 1: TTL level input
Figure 5-9. Port Control Register
6/2/98
5-5
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB 7
Reserved
Reserved INT0 Pol
Reserved
Reserved
Reserved
Reserved
INT1 Pol
INT0 Pol
LSB 0
Address: 001116 Access: R/W Reset: 0016
INT1 Pol
Bits 2-7
INT0 Interrupt Edge Selection Bit 0: Falling edge selected. 1: Rising edge selected. INT1 Interrupt Edge Selection Bit 0: Falling edge selected. 1: Rising edge selected. Reserved (Read/Write "0")
Figure 5-10. IPOL Configuration
MSB 7
PUP27
PUP26 PUP20 PUP21 PUP22 PUP23 PUP24 PUP25 PUP26 PUP27
PUP25
PUP24
PUP23
PUP22
PUP21
PUP20
LSB 0
Address: 001216 Access: R/W Reset: 0016
Pull-up Control for Port 2 (bit 0) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 1) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 2) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 3) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 4) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 5) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 6) 0: Disabled 1: Enabled Pull-up Control for Port 2 (bit 7) 0: Disabled 1: Enabled
Figure 5-11. Pull-up Control Register
MSB 7
USBC7
USBC6 Bit 0 USBC1
USBC5
USBC4
USBC3
Reserved
USBC1
Reserved
LSB 0
Address: 001316 Access: R/W Reset: 0016
Reserved (Read/Write "0") USB Default State Selection Bit (bit 1) 0: In default state after powerup/reset 1: In default state after received the USB reset signaling Reserved (Read/Write "0") Transceiver Voltage Converter High/Low Current Mode Selection Bit (bit 3) 0: High current mode 1: Low current mode USB Transceiver Voltage Converter Enable Bit (bit 4) 0: USB transceiver voltage converter disabled 1: USB transceiver voltage converter enabled USB Clock Enable Bit (bit 5) 0: 48 MHz clock to the USB block is disabled. 1: 48 MHz clock to the USB block is enabled. USB SOF Port Select Bit (bit 6) 0: USB SOF output is disabled. P70 is used as GPIO pin. 1: USB SOF output is enabled USB Enable Bit (bit 7) 0: USB block is disabled, all USB internal registers are held at their default values. 1: USB block is enabled
Bit 2 USBC3
USBC4
USBC5
USBC6
USBC7
Figure 5-12. USB Control Register
5-6
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
CCR7
CCR6 Bits 0-3 CCR4:
CCR5
CCR4
Reserved
Reserved
Reserved
Reserved
LSB 0
Address: 001F16 Access: R/W Reset: 0016
CCR5:
CCR6:
CCR7:
Reserved (Read/Write "0") PLL Bypass Bit (bit 4) 0: fUSB = fVCO (Frequency synthesizer output) 1: fUSB = fXin XCout Oscillation Drive Disable Bit (bit 5) 0: XCout oscillation drive is enabled (when XCin oscillation is enabled). 1: XCout oscillation drive is disabled. Xout Oscillation Drive Disable Bit (bit 6) 0: Xout oscillation drive is enabled (when Xin oscillation is enabled). 1: Xout oscillation drive is disabled. Xin Divider Select Bit (bit 7) 0: fXin/2 is used for the system clock source when CMPA7:6=00 1: fXin is used for the system clock source when CMPA7:6=00
Figure 5-13. Clock Control Register
Address: 002716 Access: R/W Reset: 0016
MSB 7
TXM7
TXM6 TXM0
TXM5
TXM4
TXM3
TXM2
TXM1
TXM0
LSB 0
TXM2,1
TXM3
TXM5,4
TXM6
TXM7
Timer X Data Write Control Bit (bit 0) 0: Write data in latch and timer 1: Write data in latch only Timer X Frequency Division Ratio Bits (bits 2,1) Bit 2 Bit 1 0 0: divided by 8 0 1: divided by 16 1 0: divided by 32 1 1: divided by 64 Timer X Internal Clock Select (bit 3) 0: /n 1: SCSGCLK (from chip special count source generator) Timer X Mode Bits (bits 5,4) Bit 5 Bit 4 0 0: Timer Mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 Polarity Select Bit (bit 6) 0: For event counter mode, clocked by rising edge For pulse output mode, start from high level output For CNTR0 interrupt request, falling edge active For pulse width measurement mode, measure high period 1: For event counter mode, clocked on falling edge For pulse output mode, start from low level output For CNTR0 interrupt request, rising edge active For pulse width measurement mode, measure low period Timer X Stop Bit (bit 7) 0: Count start 1: Count stop
Figure 5-14. TXM Register
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7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB 7
TYM7
TYM6 TYM0
TYM5
TYM4
TYM3
TYM2
TYM1
TYM0
TYM1
TYM3,2
TYM5,4
TYM6
TYM7
Access: R/W Timer Y Data Write Control Bit (bit 0) Reset: 0016 0: Write data in latch and timer 1: Write data in latch only Timer Y Output Control Bit (bit 1) 0: TYOUT output disable 1: TYOUT output enable Timer Y Frequency Division Ratio Bits (bit 3,2) Bit 2 Bit 1 0 0: divided by 8 0 1: divided by 16 1 0: divided by 32 1 1: divided by 64 Timer Y Mode Bits (bits 5,4) Bit 2 Bit 1 0 0: Timer mode 0 1: Pulse period measurement mode 1 0: Event counter mode 1 1: HL pulse width measurement mode (continuously measures high period and low period) CNTR1 Polarity Select Bit (bit 6) 0: For event counter mode, clocked by rising edge For pulse period measurement mode, falling edge detection For CNTR1 interrupt request, falling edge active For TYOUT, start on high output 1: For event counter mode, clocked on falling edge For pulse period measurement mode, rising edge detection For CNTR1 interrupt request, rising edge active For TYOUT, start on low output Timer Y Stop Bit (bit 7) 0: Count start 1: Count stop
LSB 0
Address: 002816
Figure 5-15. TYM Register
MSB 7
T123M7
T123M6 T123M0
T123M5
T123M4
T123M3
T123M2
T123M1
T123M0
LSB 0
Address: 002916 Access: R/W Reset: 0016
T123M1
T123M2
T123M3
T123M4
T123M5
T123M6
T123M7
TOUT Source Selection Bit (bit 0) 0: TOUT = Timer 1 output 1: TOUT = Timer 2 output Timer 1 Stop Bit (bit 1) 0: Timer running 1: Timer stopped Timer 1 Count Source Select Bit (bit 2) 0: divided by 8 1: XCin divided by 2 Timer 2 Count Source Select Bit (bit 3) 0: Timer 1 underflow signal 1: Timer 3 Count Source Select Bit (bit 4) 0: Timer 1 underflow signal 1: divided by 8 TOUT Output Active Edge Selection Bit (bit 5) 0: Start on high output 1: Start on low output TOUT Output Control Bit (bit 6) 0: TOUT output disabled 1: TOUT output enabled Timer 1 and 2 Data Write Control Bit (bit 7) 0: Write data in latch and timer 1: Write data in latch only
Figure 5-16. T123M Register
5-8
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Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
OCHCont
SCSel ISCSel0-2
TDSel
RDYSel
PSel
ISCSel2
ISCSel1
ISCSel0
LSB 0
Address: 002B16 Access: R/W Reset: 0016
PSel
RDYSel
TDSel
SCSel
OCHCont
Internal Synchronization Clock Select Bits (bits 2,1,0) Bit 2 Bit 1 Bit 0 0 0 0: Internal Clock divided by 2. 0 0 1: Internal Clock divided by 4. 0 1 0: Internal Clock divided by 8. 0 1 1: Internal Clock divided by 16. 1 0 0: Internal Clock divided by 32. 1 0 1: Internal Clock divided by 64. 1 1 0: Internal Clock divided by 128. 1 1 1: Internal Clock divided by 256. SIO Port Selection Bit (bit 3) 0: I/O Port 1: TxD output, SCLK function SRDY Output Select Bit (bit 4) 0: I/O Port 1: SRDY signal Transfer Direction Select Bit (bit 5) 0: LSB first 1: MSB first Synchronization Clock Select Bit (bit 6) 0: External Clock 1: Internal Clock TxD Output Channel Control Bit (bit 7) 0: CMOS output 1: N-Channel open drain output
Figure 5-17. SIO Control Register 1
MSB 7
Reserved
Reserved
Reserved
Reserved
Reserved
RXDSel
CLKSEL
SLAVE
LSB 0
Address: 002C16 Access: R/W Reset: 1816
SLAVE
CLKSEL
RXDSel
Bits 3-4 Bits 5-7
Slave Mode Selection Bit (bit 0) 0: Normal mode 1: Slave mode (to enter Slave mode, bit 4 of SIO Control register 1 also needs to be set) SIO Internal Clock Selection Bit (bit 1) 0: 1: SCSGCLK SRXD Input Selection Bit (bit 2) 0: SRXD input disabled 1: SRXD input enabled Reserved (Read/Write "1") Reserved (Read/Write "0")
Figure 5-18. SIO Control Register 2
MSB 7
Reserved
Reserved SCSGM0
Reserved
Reserved
SCSGM3
SCSGM2
SCSGM1
SCSGM0
LSB 0
Address: 002F16 Access: R/W Reset: 0016
SCSGM1
SCSGM2
SCSGM3
Bits 4-7
SCSG1 Data Write Control Bit (bit 0) 0: Write data in latch and timer 1: Write data in latch only SCSG1 Count Stop Bit (bit 1) 0: Count start 1: Count stop SCSG2 Data Write Control Bit (bit 2) 0: Write data in latch and timer 1: Write data in latch only SCSGCLK Output Control Bit (bit 3) 0: SCSGCLK output disabled (SCSG1 and SCSG2 off) 1: SCSGCLK output enabled. Reserved (Read/Write "0")
Figure 5-19. SCSGM Register
6/2/98
5-9
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Address: 003016, 003816 Access: R/W Reset: 0016
MSB 7
LE1
LE0 CLK
PEN
PMD
STB
PS1
PS0
CLK
LSB 0
PS1,0
STB
PMD
PEN
LE1,0
UART Clock Selection Bit (bit 0) 0: 1: SCSGCLK Internal Clock Prescaling Selection Bits (bits 2,1) Bit 2 Bit 1 0 0: Division by 1 0 1: Division by 8 1 0: Division by 32 1 1: Division by 256 Stop Bits Selection Bit (bit 3) 0: 1 1: 2 Parity Selection Bit (bit 4) 0: Even 1: Odd Parity Enable Bit (bit 5) 0: Off 1: On Uart Character Length Selection Bits (bits 7,6) Bit 7 Bit 6 0 0: 7 bits/character 0 1: 8 bits/character 1 0: 9 bits/character 1 1: Reserved
Figure 5-20. UxMOD Register
MSB 7
Reserved
SER TCM
OER
FER
PER
RBF
TBE
TCM
LSB Address: 003216, 003A16 0 Access: R only Reset: 0316
TBE
RBF
PER
FER
OER
SER
Bit 7
Transmit-Complete (Transmission Register Empty) Flag (bit 0) 0: Data in the transmission register. 1: No data in the transmission register. TX Buffer Empty Flag (bit 1) 0: Data in the TX Buffer. 1: No data in the TX Buffer. RX Buffer Full Flag (bit 2) 0: No data in the RX Buffer. 1: Data in the RX Buffer. Receive Parity Error Flag (bit 3) 0: No receive parity error. 1: Receive parity error. Receive Framing Error Flag (bit 4) 0: No receive framing error. 1: Receive framing error. Receive Overrun Flag (bit 5) 0: No receive overrun. 1: Receive overrun. Receive Error Sum Flag (bit 6) 0: No receive error. 1: Receive error. Reserved (Read "0")
Figure 5-21. UxSTS Register
5-10
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
AME TEN
RTS_SEL CTS_SEL
TIS
RIN
TIN
REN
TEN
LSB Address: 003316,003B16 0 Access: R/W 0016
REN
TIN
RIN
TIS
CTS_SEL
RTS_SEL
AME
Transmission Enable Bit (bit 0) Reset: 0: Disable the transmit process 1: Enables the transmit process. If the transmit process is disabled (TEN cleared) during transmission, the transmit will not stop until completed. Receive Enable Bit (bit 1) 0: Disable the receive process 1: Enables the receive process. If the receive process is disabled (REN cleared) during reception, the receive will not stop until completed. Transmission Initialization Bit (bit 2) 0: No action. 1: Resets the UART transmit status register bits as well as stopping the transmission operation. The TEN bit must be set and the transmit buffer reloaded in order to transmit again. The TIN is automatically reset one cycle after TIN is set. Receive Initialization Bit (bit 3) 0: No action. 1: Clears the UART receive status flags and the REN bit. If RIN is set during receive in progress, receive operation is aborted. The RIN bit is automatically reset one cycle after RIN is set. Transmit Interrupt Source Selection Bit (bit 4) 0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set. 1: Transmit interrupt occurs when the Transmit Complete flag is set. Clear-to-Send (CTS) Enable Bit (bit 5) 0: CTS function is disabled, P86 (or P82) is used as GPIO pin. 1: CTS function is enabled, P86 (or P82) is used as CTS input. Request-to-Send (RTS) Enable Bit (bit 6) 0: RTS function is disabled, P87 (or P83) is used as GPIO pin. 1: RTS function is enabled, P87 (or P83) is used as RTS output. UART Address Mode Enable Bit (bit 7) 0: Address Mode disabled. 1: Address Mode enabled.
Figure 5-22. UxCON Register
MSB 7
RTS3 Bits 0-3 RTS3:0
RTS2
RTS1
RTS0
Reserved
Reserved
Reserved
Reserved
LSB Address: 003616, 003E16 0 Access: R/W Reset: 8016
Reserved (Read/Write "0") RTS Assertion Delay Count 3:0 (bits 7,6,5,4) 0000: No delay, RTS asserts immediately after receive operation completes. RTS asserts 8 bit-times after receive operation completes. 0001: RTS asserts 16 bit-times after receive operation completes. 0010: RTS asserts 24 bit-times after receive operation completes. 0011: . . . RTS asserts 64 bit-times after receive operation completes. 1000: . . . RTS asserts 112 bit-times after receive operation completes. 1110: RTS asserts 120 bit-times after receive operation completes. 1111:
Figure 5-23. UxRTSC Register
6/2/98
5-11
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Address: 003F16 Access: R/W 0016
MSB 7
DCI
Reserved D0UF
DRLDD
DTSC
D1SFI
D1UF
D0SFI
D0UF
LSB 0
D0SFI
D1UF
D1SFI
DTSC
DRLDD
Bit 6 DCI
Reset: DMAC Channel 0 Count Register Underflow Flag (bit 0) 0: Channel 0 transfer count register underflow has not occurred 1: Channel 0 transfer count register underflow has occurred DMAC Channel 0 Suspend (due to interrupt service request) Flag (bit 1) 0: Channel 0 transfer has not been suspended 1: Channel 0 transfer has been suspended DMAC Channel 1 Count Register Underflow Flag (bit 2) 0: Channel 1 transfer count register underflow has not occurred 1: Channel 1 transfer count register underflow has occurred DMAC Channel 1 Suspend (due to interrupt service request) Flag (bit 3) 0: Channel 1 transfer has not been suspended 1: Channel 1 transfer has been suspended DMAC Transfer Suspend Control Bit (bit 4) 0: Only burst transfers are suspended during interrupt servicing 1: Both burst and single-byte transfers are suspended during interrupt servicing DMAC Register Reload Disable Bit (bit 5) 0: Reload of source and destination registers of both channels enabled 1: Reload of source and destination registers of both channels disabled Reserved (Read/Write "0") Channel Index Bit (bit 7) 0: Channel 0 mode, source, destination, and transfer count registers accessible 1: Channel 1 mode, source, destination, and transfer count registers accessible
Figure 5-24. DMAIS Configuration
Address: 004016 Access: R/W Reset: 0016
MSB 7
DxTMS
DxRLD DxSRID
DxDAUE
DxDWC
DxDRCE
DxDRID
DxSRCE
DxSRID
LSB 0
DxSRCE
DxDRID
DxDRCE
DxDWC
DxDAUE
DxRLD
DxTMS
DMAC Channel x Source Register Increment/Decrement Select Bit (bit 0) 0: Increment after transfer 1: Decrement after transfer DMAC Channel x Source Register Increment/Decrement Enable Bit (bit 1) 0: Increment/Decrement disabled (No change after transfer) 1: Increment/Decrement enabled DMAC Channel x Destination Register Increment/Decrement Select Bit (bit 2) 0: Increment after transfer 1: Decrement after transfer DMAC Channel x Destination Register Increment/Decrement Enable Bit (bit 3) 0: Increment/Decrement disabled (No change after transfer) 1: Increment/Decrement enabled DMAC Channel x Data Write Control Bit (bit 4) 0: Write data in reload latches and registers 1: Write data in reload latches only DMAC Channel x Disable After Count Register Underflow Enable Bit (bit 5) 0: Channel x not disabled after count register underflow 1: Channel x disabled after count register underflow DMAC Channel x Register Reload Bit (bit 6) 0: No action (Bit is always read as "0") 1: Setting to "1" causes the source, destination, and transfer count registers of channel x to be reloaded DMAC Channel x Transfer Mode Selection Bit (bit 7) 0: Single-byte transfer mode 1: Burst transfer mode
Figure 5-25. DMAxM1 Configuration
5-12
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB D0CEN D0CRR D0UMIE D0SWT D0HRS3 D0HRS2 D0HRS1 D0HRS0 7 D0HRS3,2,1,0 DMAC Channel 0 Hardware Transfer Request Source Bits (bits 3, 2, 1, 0) 0000: Disabled 0001: UART1 receive interrupt 0010: UART1 transmit interrupt 0011: TimerY interrupt 0100: External Interrupt 0 0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active) 0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active) 0111: USB EndPoint 3 IN_PKT_RDY signal (falling edge active) 1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active) 1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active) 1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active) 1011: USB EndPoint 3 OUT_PKT_RDY signal (rising edge active) 1100: MBI OBE0 signal (rising edge active) 1101: MBI IBF0(data) signal (rising edge active) 1110: SIO receive/transmit interrupt 1111: CNTR1 interrupt D0SWT DMAC Channel 0 Software Transfer Trigger (bit 4) 0: No action (Bit is always read as "0") 1: Writing "1" requests a channel 0 transfer D0UMIE DMAC Channel 0 USB and MBI Enable Bit (bit 5) 0: Disabled 1: Enabled D0CRR DMAC Channel 0 Transfer Initiation Source Capture Register Reset (bit 6) 0: No action (Bit is always read as "0") 1: Setting to "1" causes reset of the channel 0 capture register D0CEN DMAC Channel 0 Enable Bit (bit 7) 0: Channel 0 disabled 1: Channel 0 enabled
LSB 0
Address: 004116 Access: R/W Reset: 0016
Figure 5-26. DMA0M2 Configuration
MSB 7
D1CEN
D1CRR
D1UMIE
D1SWT
D1HRS3
D1HRS2
D1HRS1
D1HRS0
LSB 0
Address: 004116 Access: R/W Reset: 0016
D1HRS3,2,1,0 DMAC Channel 1Hardware Transfer Request Source Bits (bits 3, 2, 1, 0) 0000: Disabled 0001: UART2 receive interrupt 0010: UART2 transmit interrupt 0011: TimerX interrupt 0100: External Interrupt 1 0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active) 0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active) 0111: USB EndPoint 4 IN_PKT_RDY signal (falling edge active) 1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active) 1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal(rising edge active) 1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active) 1011: USB EndPoint 4 OUT_PKT_RDY signal (rising edge active) 1100: MBI OBE1 signal (rising edge active) 1101: MBI IBF1(data) signal (rising edge active) 1110: Timer1 interrupt 1111: CNTR0 interrupt D1SWT DMAC Channel 1 Software Transfer Trigger (bit 4) 0: No action (Bit is always read as "0") 1: Writing "1" requests a channel 0 transfer D1UMIE DMAC Channel 1 USB and MBI Enable Bit (bit 5) 0: Disabled 1: Enabled D1CRR DMAC Channel 1 Transfer Initiation Source Capture Register Reset (bit 6) 0: No action (Bit is always read as "0") 1: Setting to "1" causes reset of the channel 1 capture register D1CEN DMAC Channel 1 Enable Bit (bit 7) 0: Channel 1 disabled 1: Channel 1 enabled
Figure 5-27. DMA1M2 Configuration
6/2/98
5-13
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB 7
DBBS07
DBBS06 DBBS00
DBB05
DBBS04
DBBS03
DBBS02
DBBS01
DBBS00
LSB 0
Address: 004916 Access: R/W Reset: 0016
DBBS01
DBBS02 DBBS03 DBBS04 DBBS05 DBBS06 DBBS07
Output Buffer Full (OBF0) Flag (bit 0) 0: Output buffer empty. 1: Output buffer full. Input Buffer Full (IBF0) Flag (bit 1) 0: Input buffer empty. 1: Input buffer full. User Definable (U2) Flag (bit 2) A0 (A00) Flag (bit 3) Indicates the A0 status when IBF flag is set User Definable (U4) Flag (bit 4) User Definable (U5) Flag (bit 5) User Definable (U6) Flag (bit 6) User Definable (U7) Flag (bit 7)
Figure 5-28. Data Bus Buffer Status Register 0
MSB 7
DBBC07
DBBC06 DBBC00
Reserved DBBC04
DBBC03
DBBC02
DBBC01
DBBC00
LSB 0
Address: 004A16 Access: R/W
DBBC01
DBBC02
DBBC03
DBBC04
DBBC05 DBBC06
DBBC07
OBF Output Selection Bit (bit 0) Reset: 0016 0: P52 pin is operated as GPIO 1: P52 pin is operated as OBF0 output pin IBF Output Selection Bit (bit 1) 0: P53 pin is operated as GPIO 1: P53 pin is operated as IBF0 output pin IBF0 Interrupt Selection Bit (bit 2) 0: IBF0 interrupt is generated by both write-data (A0 = "0") and write-command (A0 = "1") 1: IBF0 interrupt is generated by write-command (A0 = "1") only Output buffer 0 empty interrupt disable Bit (bit 3) 0: Enabled 1: Disabled Input buffer 0 full interrupt disable Bit (bit 4) 0: Enabled 1: Disabled Reserved (Read/Write "0") Master CPU Bus Interface Enable Bit (bit 6) 0: P60-P67, P54-P57 are GPIO pins 1: P60-P67, P54-P57 are bus interface signals DQ0-DQ7, S0, A0, R, W respectively. Bus Interface Type Selection Bit (bit 7) 0: RD, WR separate type bus 1: R/W type bus.
Figure 5-29. Data Bus Buffer Control Register 0
Address: 004D16 Access: R/W Reset: 0016
MSB 7
DBBS17
DBBS16 DBBS10
DBB15
DBBS14
DBBS13
DBBS12
DBBS11
DBBS10
LSB 0
DBBS11
DBBS12 DBBS13 DBBS14 DBBS15 DBBS16 DBBS17
Output Buffer Full (OBF1) Flag (bit 0) 0: Output buffer empty. 1: Output buffer full. Input Buffer Full (IBF1) Flag (bit 1) 0: Input buffer empty. 1: Input buffer full. User Definable (U2) Flag (bit 3) A0 (A01) Flag (bit 2) Indicates the A0 status when IBF flag is set User Definable (U4) Flag (bit 4) User Definable (U5) Flag (bit 5) User Definable (U6) Flag (bit 6) User Definable (U7) Flag (bit 7)
Figure 5-30. Data Bus Buffer Status Register 1
5-14
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB DBBC17 7
Reserved DBBC10
Reserved DBBC14
DBBC11
DBBC12
DBBC13
DBBC14
DBBC15 DBBC16 DBBC17
Access: R/W OBF1 Output Selection Bit (bit 0) Reset: 0016 0: P74 pin is operated as GPIO 1: P74 pin is operated as OBF1 output pin if DBBC17 = "1" IBF1 Output Selection Bit (bit 1) 0: P73 pin is operated as GPIO 1: P73 pin is operated as IBF1 output pin if DBBC17 = "1" IBF1 Interrupt Selection Bit (bit 2) 0: IBF1 interrupt is generated by both write-data (A0 = "0") and write-command (A0 = "1") 1: IBF1 interrupt is generated by write-command (A0 = "1") only Output Buffer 1 Empty interrupt disable Bit (bit 3) 0: Enabled 1: Disabled Input Buffer 1 Full interrupt disable Bit (bit 4) 0: Enabled 1: Disabled Reserved (Read/Write "0") Reserved (Read/Write "0") Data Bus Buffer Function Selection Bit (bit 7) 0: Single data bus buffer - P72 is used as GPIO 1: Double data bus buffer - P72 is used as S1 input
DBBC13
DBBC12
DBBC11
DBBC10
LSB 0
Address: 004E16
Figure 5-31. Data Bus Buffer Control Register 1
MSB 7
Reserved
FUNAD6 FUNAD6:0 Bit 7
FUNAD5
FUNAD4
FUNAD3
FUNAD2
FUNAD1
FUNAD0
LSB 0
Address: 005016 Access: R/W Reset: 0016
7-bit programmable Function Address (bits 6-0) Reserved (Read/Write "0")
Figure 5-32. Function Address Register
MSB 7
Reserved
Reserved SUSPEND
Reserved
Reserved
Reserved
WAKEUP
RESUME SUSPEND LSB 0
Address: 005116 Access: R/W Reset: 0016
RESUME
WAKEUP
USB Suspend Detection Flag (bit 0) (Write "0" only or Read) 0: No USB suspend signal detected 1: USB suspend signal detected USB Resume Detection Flag (bit 1) (Write "0" only or Read) 0: No USB resume signal detected 1: USB resume signal detected USB Remote Wake-up Bit (bit 2) 0: End remote resume signaling 1: Remote resume signaling (If SUSPEND = "1") Reserved (Read/Write "0")
Bit7:3
Figure 5-33. Power Management Register
MSB 7
INTST7
INTST6 INTST0 Bit 1 INTST2 INTST3 INTST4 INTST5 INTST6 INTST7
INTST5
INTST4
INTST3
INTST2
Reserved
INTST0
LSB 0
Address: 005216 Access: R/W Reset: 0016
USB Endpoint 0 Interrupt Status Flag (bit 0) Reserved (Read/Write "0") USB Endpoint 1 IN Interrupt Status Flag (bit 2) USB Endpoint 1 OUT Interrupt Status Flag (bit 3) USB Endpoint 2 IN Interrupt Status Flag (bit 4) USB Endpoint 2 OUT Interrupt Status Flag (bit 5) USB Endpoint 3 IN Interrupt Status Flag (bit 6) USB Endpoint 3 OUT Interrupt Status Flag (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 5-34. Interrupt Status Register 1
6/2/98
5-15
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB 7
INTST15
INTST14 INTST8 INTST9 Bit 3:2 INTST12 INTST13 INTST14 INTST15
INTST13
INTST12
Reserved
Reserved
INTST9
INTST8
LSB 0
Address: 005316 Access: R/W Reset: 0016
USB Endpoint 4 In Interrupt Status Flag (bit 0) USB Endpoint 4 Out Interrupt Status Flag (bit 1) Reserved (Read/Write "0") USB Overrun/Underrun Interrupt Status Flag (bit 4) USB Reset Interrupt Status Flag (bit 5) USB Resume Signaling Interrupt Status Flag (bit 6) USB Suspend Signaling Interrupt Status Flag (bit 7) 0: No interrupt request issued 1: Interrupt request issued
Figure 5-35. Interrupt Status Register 2
MSB 7
INTEN7
INTEN6 INTEN0 Bit 1 INTEN2 INTEN3 INTEN4 INTEN5 INTEN6 INTEN7
INTEN5
INTEN4
INTEN3
INTEN2
Reserved
INTEN0
LSB 0
Address: 005416 Access: R/W Reset: FF16
USB Endpoint 0 In Interrupt Enable Bit (bit 0) Reserved (Read/Write "0") USB Endpoint 1 IN Interrupt Enable Bit (bit 2) USB Endpoint 1 OUT Interrupt Enable Bit (bit 3) USB Endpoint 2 IN Interrupt Enable Bit (bit 4) USB Endpoint 2 OUT Interrupt Enable Bit (bit 5) USB Endpoint 3 IN Interrupt Enable Bit (bit 6) USB Endpoint 3 OUT Interrupt Enable Bit (bit 7) 0: Interrupt disabled 1: Interrupt enabled
Figure 5-36. Interrupt Enable Register 1
MSB 7
INTEN15
Reserved INTEN8 INTEN9 Bit 3:2 INTEN12 INTEN13 Bit 6 INTEN15
INTEN13
INTEN12
Reserved
Reserved
INTEN9
INTEN8
LSB 0
Address: 005516 Access: R/W Reset: 3316
USB Endpoint 4 IN Interrupt Enable Bit (bit 0) USB Endpoint 4 OUT Interrupt Enable Bit (bit 1) Reserved (Read/Write "0") USB Overrun/Underrun Interrupt Enable Bit (bit 4) USB Reset Interrupt Enable Bit (bit 5) Reserved (Read/Write "0") USB Suspend/Resume Signaling Interrupt Enable Bit (bit 7) 0: Interrupt disabled 1: Interrupt enabled
Figure 5-37. Interrupt Enable Register 2
MSB 7
FN7
FN6 FN7:0
FN5
FN4
FN3
FN2
FN1
FN0
LSB 0
Address: 005616 Access: R Reset: 0016
Lower 8 bits of the 11-bit frame number issued with a SOF token
Figure 5-38. Frame Number Register Low
MSB 7
Reserved
Reserved FN10:8 Bits 7:3
Reserved
Reserved
Reserved
FN10
FN9
FN8
LSB 0
Address: 005716 Access: R Reset: 0016
Upper 3 bits of the 11-bit frame number issued with a SOF token Reserved (Read "0")
Figure 5-39. Frame Number Register High
5-16
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
ISO_UPD AUTO_FL EPINDX2:0
Reserved
Reserved
Reserved Bit 0 0: 1: 0: 1: 0:
EPINDX2 EPINDX1 EPINDX0 LSB 0
Address: 005816 Access: R/W Reset: 0016
Endpoint Index: Bit 2 Bit 1 0 0 0 0 0 1 0 1 1 0 Others:
Function Endpoint 0 Function Endpoint 1 Function Endpoint 2 Function Endpoint 3 Function Endpoint 4 Undefined
Bits 3:5 AUTO_FL
Reserved (Read/Write "0") AUTO_FLUSH Bit (bit 6) 0: Hardware auto FIFO flush disabled 1: Hardware auto FIFO flush enabled ISO_UPDATE Bit (bit 7) 0: ISO_UPDATE disabled 1: ISO_UPDATE enabled
ISO_UPD
Figure 5-40. Endpoint Index Register
MSB 7
IN0CSR7
IN0CSR6 IN0CSR0
IN0CSR5
IN0CSR4
IN0CSR3
IN0CSR2
IN0CSR1
IN0CSR0
LSB 0
Address: 005916 Access: R/W Reset: 0016
IN0CSR1
IN0CSR2
IN0CSR3
IN0CSR4
IN0CSR5
IN0CSR6
IN0CSR7
OUT_PKT_RDY Flag (bit 0) (Read Only - Write "0") 0: Out packet is not ready 1: Out packet is ready IN_PKT_RDY Bit (bit 1) (Write "1" only or Read) 0: In packet is not ready 1: In packet is ready SEND_STALL Bit (bit 2) (Write "1" only or Read) 0: No action 1: Stall Endpoint 0 by the CPU DATA_END Bit (bit 3) (Write "1" only or Read) 0: No action 1: Last packet of data transferred from/to the FIFO FORCE_STALL Flag (bit 4) (Write "0" only or Read) 0: No action 1: Stall Endpoint 0 by the USB FCU SETUP_END Flag (bit 5) (Read Only - Write "0") 0: No action 1: Control transfer ended before the specific length of data is transferred during the data phase SERVICED_OUT_PKT_RDY Bit (bit 6) (Write Only - Read "0") 0: No change 1: Clear the OUT_PKT_RDY bit (IN0CSR0) SERVICED_SETUP_END Bit (bit 7) (Write Only - Read "0") 0: No change 1: Clear the STUP_END bit (IN0CSR5)
Figure 5-41. Endpoint 0 IN CSR
6/2/98
5-17
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB 7
INXCSR7 INXCSR6 INXCSR5 INXCSR4 INXCSR3 INXCSR2 INXCSR1 INXCSR0 LSB 0 INXCSR0 IN_PKT_RDY Bit (bit 0) (Write "1" only or Read) 0: In packet is not ready 1: In packet is ready UNDER_RUN Flag (bit 1) (Write "0" only or Read) 0: No FIFO underrun 1: FIFO underrun has occurred SEND_STALL Bit (bit 2) 0: No action 1: Stall IN Endpoint X by the CPU ISO Bit (bit 3) 0: Select non-isochronous transfer 1: Select isochronous transfer INTPT Bit (bit 4) 0: Select non-rate feedback interrupt transfer 1: Select rate feedback interrupt transfer TX_NOT_EPT Flag (bit 5) (Read Only - Write "0") 0: Transmit FIFO is empty 1: Transmit FIFO is not empty FLUSH Bit (bit 6) (Write Only - Read "0") 0: No action 1: Flush the FIFO AUTO_SET Bit (bit 7) 0: AUTO_SET disabled 1: AUTO_SET enabled
Address: 005916 Access: R/W Reset: 0016
INXCSR1
INXCSR2
INXCSR3
INXCSR4
INXCSR5
INXCSR6
INXCSR7
Figure 5-42. Endpoints 1, 2, 3, 4 IN CSR
MSB 7
Reserved
Reserved Bits 7:0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LSB 0
Address: 005A16 Access: R Reset: 0016
Reserved (Read "0")
Figure 5-43. Endpoint 0 OUT CSR
MSB 7
OUTXCSR7 OUTXCSR6 OUTXCSR5 OUTXCSR4 OUTXCSR3 OUTXCSR2 OUTXCSR1 OUTXCSR0 LSB
Address: 005A16 Access: R/W Reset: 0016
0
OUTXCSR0
OUTXCSR1
OUTXCSR2
OUTXCSR3
OUTXCSR4
OUTXCSR5
OUTXCSR6
OUTXCSR7
OUT_PKT_RDY Flag (bit 0) (Write "0" only or Read) 0: Out packet is not ready 1: Out packet is ready OVER_RUN Flag (bit 1) (Write "0" only or Read) 0: No FIFO overrun 1: FIFO overrun occurred SEND_STALL Bit (bit 2) 0: No action 1: Stall OUT Endpoint X by the CPU ISO Bit (bit 3) 0: Select non-isochronous transfer 1: Select isochronous transfer FORCE_STALL Flag (bit 4) (Write "0" only or Read) 0: No action 1: Stall Endpoint X by the USB FCU DATA_ERR Flag (bit 5) (Write "0" only or Read) 0: No error 1: CRC or bit stuffing error received in an ISO packet FLUSH Bit (bit 6) (Write Only - Read "0") 0: No action 1: Flush the FIFO AUTO_CLR Bit (bit 7) 0: AUTO_CLR disabled 1: AUTO_CLR enabled
Figure 5-44. Endpoint 1, 2, 3, 4 OUT CSR
5-18
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
IMAXP7
IMAXP6 IMAXP7:0
IMAXP5
IMAXP4
IMAXP3
IMAXP2
IMAXP1
IMAXP0
LSB 0
Address: 005B16 Access: R/W
Maximum packet size (MAXP) of Endpoint x IN packet. MAXP = n for endpoints 0, 2, 3, 4 MAXP = n * 8 for endpoint 1 n is the value written to this register. For endpoints that support a smaller FIFO size, unused bits are not implemented (always write "0" to those bits)
Figure 5-45. Endpoint x IN MAXP
MSB 7
OMAXP7
OMAXP6 OMAXP7:0
OMAXP5
OMAXP4
OMAXP3
OMAXP2
OMAXP1
OMAXP0 LSB 0
Address: 005C16 Access: R/W
Maximum packet size (MAXP) of Endpoint x OUT packet. MAXP = n for endpoints 2, 3, 4 MAXP = n * 8 for endpoint 1 n is the value written to this register. For endpoints that support a smaller FIFO size, unused bits are not implemented (always write "0" to those bits)
Figure 5-46. Endpoint x OUT MAXP
MSB 7
W_CNT7
W_CNT6 W_CNT7:0
W_CNT5
W_CNT4
W_CNT3
W_CNT2
W_CNT1
W_CNT0
LSB 0
Address: 005D16 Access: R Reset: 0016
Byte Count. This register contains the lower 8 bits of the byte count register
Figure 5-47. Endpoint 0, 1, 2, 3, 4 OUT Write Count Register Low
MSB 7
Reserved
Reserved W_CNT9:8 Bits 7:2
Reserved
Reserved
Reserved
Reserved
W_CNT9
W_CNT8
LSB 0
Address: 005E16 Access: R Reset: 0016
Byte Count. This register contains the upper 2 bits of the byte count register Reserved (Read "0")
Figure 5-48. Endpoint 0, 1, 2, 3, 4 OUT Write Count Register High
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006016 Access: R/W Reset: N/A
Endpoint 0 IN/OUT FIFO register
Figure 5-49. Endpoint 0 FIFO Register
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006116 Access: R/W Reset: N/A
Endpoint 1 IN/OUT FIFO register
Figure 5-50. Endpoint 1 FIFO Register
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006216 Access: R/W Reset: N/A
Endpoint 2 IN/OUT FIFO register
Figure 5-51. Endpoint 2 FIFO Register
6/2/98
5-19
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006316 Access: R/W Reset: N/A
Endpoint 3 IN/OUT FIFO register
Figure 5-52. Endpoint 3 FIFO Register
MSB 7
DATA_7
DATA_6 DATA_7:0
DATA_5
DATA_4
DATA_3
DATA_2
DATA_1
DATA_0
LSB 0
Address: 006416 Access: R/W Reset: N/A
Endpoint 4 IN/OUT FIFO register
Figure 5-53. Endpoint 4 FIFO Register
MSB 7
LS
CHG1 FSE
CHG0
Reserved
FIN
VCO1
VCO0
FSE
LSB 0
VCO1,0
FIN
Bit 4 CHG1,0
LS
Frequency Synthesizer Enable Bit (bit 0) 0: Disabled 1: Enabled VCO Gain Control (bits 2,1) Bit 2 Bit 1 0 0: Lowest Gain (recommended) 0 1: Low Gain 1 0: High Gain 1 1: Highest Gain Frequency Synthesizer input selector Bit (bit 3) 0: Xin 1: XCin Reserved (Read/Write "0") LPF Current Control (bits 6,5) Bit 6 Bit 5 0 0: Disabled 0 1: Low Current 1 0: Intermediate Current (recommended) 1 1: High Current Frequency Synthesizer Lock Status Bit (bit 7) (Read Only; Write "0") 0: Unlocked 1: Locked
Address: 006C16 Access: R/W Reset: 6016
Figure 5-54. Frequency Synthesizer Control Register
MSB 7
Bit 7
Bit 6 fPIN
Bit 5
Bit 4 FSM1 Dec(n) 74 11 5 3 1
Bit 3
Bit 2
Bit 1 fVCO
Bit 0
Address: 006D16 LSB Access: R/W 0 Reset: FF16
Hex(n) 4A 0B 05 03 01
320 kHz 2 MHz 4 MHz 6 MHz 12 MHz 24 MHz
48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz 48.00 MHz
0 00 fVCO/2(n+1) = fPIN
Figure 5-55. Frequency Synthesizer Multiply Control register FSM1
5-20
6/2/98
Mitsubishi Microcomputer
7600 Series M37640E8-XXXF Preliminary Specification
MSB 7
Bit 7
Bit 6
Bit 5
Bit 4 FSM2 Dec(n) 255 11 5 3 1
Bit 3
Bit 2
Bit 1
Bit 0
LSB 0
Address: 006E16 Access: R/W Reset: FF16
fPIN 24 MHz 1 MHz 2 MHz 3 MHz 6 MHz 12 MHz
Hex(n) FF 0C 05 03 01
fIN 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz 24.00 MHz
0 00 fIN/2(n+1) = fPIN
Figure 5-56. Frequency Synthesizer Multiply Control Register FSM2
MSB 7
Bit 7
Bit 6 fVCO
Bit 5
Bit 4 FSD Dec(m) 00
Bit 3
Bit 2
Bit 1 fSYN
Bit 0
LSB Address: 006F16 0 Access: R/W Reset: FF16
Hex(m) 00
48.00 MHz 48.00 MHz
24.00 MHz 187.50 KHz
127 7F fVCO/2(m+1) = fSYN
Figure 5-57. Frequency Synthesizer Divide Register
6/2/98
5-21
7600 Series M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
5-22
6/2/98

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